Specification Update 35
Errata
Implication: Unexpected behavior may occur due to the incorrect value of the RIP on the stack.
Specifically, return from the event handler via IRET may encounter an unexpected page
fault or may begin fetching from an unexpected code address.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ71. A String Instruction that Re-maps a Page May Encounter an
Unexpected Page Fault
Problem: An unexpected page fault (#PF) may occur for a page under the following conditions:
Implication: Software may see an unexpected page fault that indicates that there is no translation
for the page. Intel has not observed this erratum with any commercially-available
software or system.
• The paging structures initially specify a valid translation for the page.
• Software modifies the paging structures so that there is no valid translation for the
page (e.g., by clearing to 0 the present bit in one of the paging-structure entries
used to translate the page).
• An iteration of a string instruction modifies the paging structures so that the
translation is again a valid translation for the page (e.g., by setting to 1 the bit that
was cleared earlier).
• A later iteration of the same string instruction loads from a linear address on the
page.
• Software did not invalidate TLB entries for the page between the first modification
of the paging structures and the string instruction. In this case, the load in the later
iteration may cause a page fault that indicates that there is no translation for the
page (e.g., with bit 0 clear in the page-fault error code, indicating that the fault was
caused by a not-present page).
Workaround:Software should not update the paging structures with a string instruction that
accesses pages mapped the modified paging structures.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ72. Logical Processor May Use Incorrect VPID after VM Entry That Returns
From SMM
Problem: A logical processor in VMX root operation should use VPID 0000H. Due to this erratum,
a logical processor may instead use VPID 1FB3H if VMX root operation was entered
using a VM entry that returns from SMM.
Implication: After a VM entry that sets the "enable VPID" VM-execution control and that establishes
VPID 1FB3H, the logical processor may erroneously use TLB entries that were cached in
VMX root operation.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ73. MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost
Technology Core Ratio Multipliers for Non-Existent Core
Configurations
Problem: MSR_TURBO_RATIO_LIMIT MSR (1ADH) is designed to describe the maximum Intel
Turbo Boost Technology potential of the processor. On some processors, a non-zero
Intel Turbo Boost Technology value will be returned for non-existent core
configurations.
Implication: Due to this erratum, software using the MSR_TURBO_RATIO_LIMIT MSR to report Intel
Turbo Boost Technology processor capabilities may report erroneous results.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
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