JBL PARTYBOX 110 - Circuit Schematics - Main Board; ADC and Audio Output Sections

To TLV320ADC5410
ADC SECTION
ADC Input Impedance 2.5K,120dB SNR
ADC 1Vrms Overload,OP Weaken Analog signal
I2C Adress:0,0
ADC_I2S OUT
From MLC3740
AUX IN
MIC IN
From MLC3740
A
B
C
D
123456
D
C
B
A
1
V+
2
NO1
7
NC2
6
GND
8
IN2
9
COM2
10
NO2
5
NC1
4
IN1
3
COM1
U13
SD20
5  
5  
R256 100K

5

5  
5


5  
5  
5  
5  
&
9;5 Q)
&
9;5 X)
5
VNEG
6
OUTL
7
OUTR
8
AVDD
9
AGND
10
VCOM
11
SDA
12
SCL
13
GPIO5
14
GPIO4
15
GPIO3
16
ADR2
17
MODE1
18
MODE2
19
GPIO6
20
SCK
21
BCK
22
DIN
23
LRCK
24
ADR1
4
CAPM
3
CPGND
2
CAPP
1
CPVDD
28
DVDD
27
DGND
26
LDO0
25
XSMT
U26
PCM5121
R147 100K

R148 100K

R149 10K

R152 10K

R266 100K

R268 NC

R269 10K

&
9;5 Q)
&
9;5 X)
&
9;5 Q)
&
9;5 X)
&
9 ;5
X)
&
9 ;5
Q)
&
9 ;5
X)
R2700

R2710

R2720

R273 NC

L18
1K@100MHz
500mA
0402
R274 4.7K

R275 4.7K

R276 10K

R277 470

R278 470

&
9;5 Q)
R279 NC

&
9;5 Q)
&
9;5 X)
R281 0
Phz0$;
&
9;5 Q)
R286 NC

R289100K

R290100K

R2912.2

R292 0

R293 0

R2940

R295 1K

R296 NC

R297 0R
5 
5 
&
9;5
X)
&
9;5
X)
& 100nF
9;5
& 100nF
9;5
& X)
9;5
& X)
9;5
& 100nF
9;5
&X)
9 ;5
&X)
9 ;5
& 100nF
9;5
& 1&
9;5
&
100nF
9 ;5
& X)
9;5
& X)
9;5
& X)
9;5
& X)
9;5
& X)
9;5
& X)
9;5
&
10uF
9 ;5
&
10uF
9 ;5
&
10uF
9 ;5
R548 0R
Phz0$;
R549 0R
Phz0$;
&
10uF 9;5
R550 4.7K

R551 4.7K

R556
10K

R557NC

R558NC

R559 0

R560 0

R561NC

1
AVDD
2
AREG
3
VREF
4
AVSS
5
MICBIAS
6
IN1P_GPI1
7
IN1M_GPIO2
8
IN2P_GPI2
9
N2M_GPIO3
10
IN3P_GPI3
11
IN3M_GPIO4
12
IN4P_GPI4
13
IN4M_GPIO5
14
SHDNZ
15
ADDR1_MISO
16
ADDR0_SCLK
17
SCL_MOSI
18
SDA_SSZ
19
IOVDD
20
GPIO1
21
SDOUT
22
BCLK
23
FSYNC
24
DREG
0
GDN-PAD
U23
TLV320ADC5140
& NC
9;5
R552 33

R553 33

R554 33

R555 33

R123 NC

R228 NC

AGND
A_SW
A_SW
AGND
AUX_IN_L
AUX_IN_R
USB_L
USB_R
L_OUT
R_OUT
AGND AGND
VCC_4V7_ANALOG
PCM1_BCLK
USB/BT_DATA
PCM1_LRCLK
VCC_3V3_ANALOG
SYS_3V3
USB_R
USB_L
VCC_3V3_ANALOG
AGND
AGND
PCM1_SDA
PCM1_SCL
PCM1_MUTE
PCM1_LRCLK
PCM1_BCLK
MLC_LRCLK
MLC_BCLK
VCC_3V3_ANALOG
VCC_3V3_ANALOG
L_OUT
MIC1_P
TLV_PDN
TLV_SDA
TLV_SCL
TLV_DATA
MLC_BCLK
MLC_LRCLK
GND
GND
R_OUT
TLV_DATA1
0$,1%2$5'