JVC CH-X400 - Page 30

CH-X400/CH-X450
1-30
UPD780058GC-067(IC601):CPU
2.Block diagram
1.Terminal layout
80 61
21 40
1
20
60
41
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT12
PORT13
REAL-TIME
OUTPUT PORT
EXTERNAL
ACCESS
SYSTEM
CONTROL
P00
P01-P06
P07
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
TO1/P31
TI1/P33
TO2/P32
TI2/P34
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
S12/RXD/P70
SO2/TXD/P71
SCK2/ASCK/72
ANI0/P10-
ANI7/P17
ANO0/P130
ANO1/P131
AV
33
AV REF0
AVss
AV
REF1
INTP0/P00-
INTPS/P05
PCL/P35
BUZ/P36
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P72
P120-P127
P130-P131
RESET
X1
X2
XT1/P07
XT2
RTP0/P120-
RTP7/P127
RTP0/P120-
RTP7/P127
A8/P50-
A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
V00 Vss IC
BUZZER OUTPUT
INTERRUPT
CONTROL
D/A CONVERTER
A/D CONVERTER
SERIAL
INTERFACE2
SERIAL
INTERFACE1
SERIAL
INTERFACE0
WATCH TIMER
WATCDOG TIMER
8-bit TIMER/
EVENT COUNTER2
8-bit TIMER/
EVENT COUNTER1
16-bit TIMER/
EVENT COUNTER1
CLOCK OUTPUT
CONTROL
78K/0
CPU CORE
ROM
RAM
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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