JVC GR-SXM277UA - Page 92

5
4
3
2
1
A
BC
D
S_DET
CAMERA AND Y/C SYSTEM BLOCK DIAGRAM (2/2)
CN25
Y
C
139
220
SVHSOUT
PBFMI (AINT)
ENCODER
Y
LPF
REC
YNR
D. E
Y
PBREC
Y
PB
S_ET
LPF
REC
PBREC
FF
CLAMP
Y
Y
LNC
PBYNR
NC/PC2
MUTE
CTL
GAIN
PC1
Y
Y
MOD
FM
H SW
CTL
GAIN
Y
FB
CLAMP
Y
SYNC
SEP
PBREC
CHROMA
LOGIC
SYNC
ADD
Y
CLIP
Y
REC
Y :8bit
REC_Y
C :4bit
10bit
PB
(Y+C)
PB_C
CBI
DICK
NRBIN
HPF
ACC
CC
BURST ADD
P.BURST ADD
C
C
BURST
EMPH
T
REC
PB
C
LPF
C
DET
ACC
PB
REC
HiFi
TRAP
C
A/D HPF
FM
DEMO
DO
DET
MUTE
CTL
GAIN
C
DET
APC
CNR
L
C
COMB
DECODER
C
Chroma
Logic
BURST
DE_EMPH
P.BURST
ERASE
MUTE
GAIN
CTL
I/F
C
NRB_OUT
DOCK
CPO0
SO3
SCK3
V_PB_C
Y
CPO3
Y
FROM
CPU
N.L DE_EMPH
I/F
161
160
2
18
Y+C
6
Q4701
BUF
BWYOUT
TO BWVF
BWY0
146
TO LCD
169
147
168
SUB CARRIER
+
C
Y
YOUT
COUT
BLK
MOD
MOD
LPF
LIM
CAM_Y
BUF
BUF
CONV
D/A
CONV
B-Y
BUF
CONV
D/A
R-Y
Y
D/A
CLAMP
CLAMP
MODULE
BUF
BUF
JIG_CONN.
V OUT
DA_G_
DA_B
DA_R_
SUB DE_EMPH
N.L EMPH
SUB EMPH
MAIN
DE_EMPH
MAIN EMPH
W/D CLIP
CAM_C
V_ASP_CS
IC4701
(V-OUT)
Y/C
MIX
4
Q4702
BUF
Y
Q3505
SW
S_DET+
Y/C MIX
&6dB AMP
2
7
12
15
9
Y+C
2FSC
C_SYNC B
DSP CONTROL
INTER FACE
C
a
V_PB_C
C
IC4001(DSP)
IC47
0
(V-O
U
S_DET_L
V_PB_F
2-49