UX-M5R
1-23
68
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74
75
76
77
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84
85
86
87
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90
91
92
93
94
95
96
97
98
99
100
DMOUT
CKSE
DACT
TESIN
TESIO1
VSS4
PXI
PXO
VDD4
XVSS
XI
XO
XVDD
DVSR
RO
DVDD
DVR
LO
DVSL
TEST1
TEST2
TEST3
BUS0
BUS1
BUS2
BUS3
VDD5
VSS5
BUCK
CCE
TEST4
TSMOD
RST
I
I
I
I
I
-
I
O
-
-
I
O
-
-
O
-
-
O
-
I
I
I
I/O
I/O
I/O
I/O
-
-
I
I
I
I
I
Pin No. Symbol I/O
This terminal controls IO0 IO3 terminal. At "L" level time, IO0, 1 out feed
equalizer signal of 2-state PWM, IO2,3 out disk equalizer signal of 2-state PWM.
Normally, keep at open.
DAC test mode terminal. Normally, keep at open.
Test input terminal. Normally, keep at "L" level.
Test input/output terminal. Normally, keep at "L" level.
Digital ground terminal.
Crystal oscillator connecting input terminal for DSP. Normally, keep at "L" level.
Crystal oscillator connecting output terminal for DSP.
Digital power supply voltage terminal.
Oscillator ground terminal for system clock.
Crystal oscillator connecting input terminal for system clock.
Crystal oscillator connecting output terminal for system clock.
Oscillator power supply voltage terminal for system clock.
Analog ground terminal for DA converter.(R-ch)
R channel data forward output terminal.
Analog supply voltage terminal for DA converter.
Reference voltage terminal for DA converter.
L channel data forward output terminal.
Analog ground terminal for DA converter.(L-ch)
Test mode terminal. Normal, keep at open.
Test mode terminal. Normal, keep at open.
Test mode terminal. Normal, keep at open.
Micon interface data input/output terminal.
Digital power supply voltage terminal.
Digital ground terminal.
Micon interface clock input terminal.
Command and data sending/receiving chip enable signal input terminal.
The bus line becomes active at "L" level.
Test mode terminal. Normal, keep at open.
Local test mode selection terminal.
Reset signal input terminal. Reset at "L" level.
Function
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