JVC XV-521BK - Page 37

XV-521BK/523GD/525BK/421BK
1-37
I/O
I/O
I/O
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I/O
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I/O
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I/O
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I/O
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I/O
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I/O
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I/O
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I/O
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I/O
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I/O
O
O
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O
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O
O
O
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O
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O
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O
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O
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O
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O
I/O
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I/O
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O
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
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50
Programmable I/O pins. Output mode after reset
3.3-V supply voltage for I/O signals.
Programmable I/O pins. Output mode after reset
Ground for core logic and I/O signals.
No Connection
Programmable I/O pins. Input mode after reset
Memory data
Memory data
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
2.5-V supply voltage for core logic.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
SDRAM LDQM.
SDRAM UDQM.
3.3-V supply voltage for I/O signals.
SDRAM write enable. Decoder asserts active LOW to request a write operation to the
SDRAM array.
Ground for core logic and I/O signals.
SDRAM system clock.
Active LOW SDRAM column address.
Active LOW SDRAM row address.
3.3-V supply voltage for I/o signals.
Active LOW SDRAM bank select.
Ground for core logic and I/O signals.
Active LOW SDRAM bank select.
2.5-V supply voltage for core logic.
No Connection.
Ground for core logic and I/O signals.
No Connection.
3.3-V supply voltage for I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
Pin No.
Symbol
PIO1
MDATA15
M DATA0
VDD-3.3
MDATA14
VSS
M DATA1
MDATA13
M DATA2
VDD-3.3
MDATA12
VSS
M DATA3
VDD-2.5
MDATA11
VSS
M DATA4
VDD-3.3
MDATA10
VSS
M DATA5
M DATA9
M DATA6
VDD-3.3
M DATA8
VSS
M DATA7
LDQM
UDQM
VDD-3.3
MWE
VSS
SD-CLK
SD-CAS
SD-RAS
VDD-3.3
SD-CS1
VSS
SD-CS0
VDD-2.5
NC
VSS
NC
VDD-3.3
MADDR9
VSS
MADDR11
PIO28
PIO29
PIO30
VDD-3.3
PIO31
VSS
NC
I/O
Function
ZIVA3-PEO (2/5)