JVC XV-N50BK - Parental Lock Setup Procedure

XV-N50BK,XV-N55SL
(No.A0041)1-31
4.6 K4S643232E-TC60(IC505):DRAM
• Block diagram
• Pin function
Bank select
Address register
Row buffer
refresh counter
LRAS
LRAS
LCBR
LCBR LWE
CLK
A
DD
LCKE
Row decoder
Col. buffer
LCAS LWCBR
CLK CKE CS RAS CAS WE DQM
LDQM
Timing register
Data input register
512K x 32
512K x 32
512K x 32
512K x 32
I/O control
Sense AMP
Output buffer
LWE
LDQM
DQI
Column decoder
Latency & burst length
Programming register
Symbol Description
CLK System clock signal input
CS Chip select input
CKE Clock enable
A0~A10 Address
BA0,1 Bank select address
RAS Row address strobe
CAS Column address strobe
WE Write enable
DQM0~3 Data input/output mask
DQ0~31 Data input/output
VDD Power supply terminal
VSS Connect to ground
VDDQ Power supply terminal
VSSQ Connect to ground
NC Non connect