KDK FM-2016A - Main Unit

7, CIRCUIT DESCRIPTION
PLEASE
REFER
TO
BLOCK
DIAGRAM
ON
PAGE
12
AND
THE
SCHEMATIC
WHEN
RNADING
THIS
SECTION.
(A) GENERAL
The
receiver
first
local
oscillator
is
the
VCO
controlled
by
the
PLL
to
provide
the
correct
injection
frequency
to
the
mixer.
The
receiver
is
of
the
double
con-
version
superheterodyne
type
with
a
lst
IF
of
16.9MHz
and
a
2nd
IF
of
455KHz.
The
transmitter
is
a
single
conversion
type
mixing
the
output
from
a
16.9MHz
osci-
liator
with
the
output
fromthe
VCO,
with
modulation
being
applied
directly
to
the
VCO.
(B) MAIN UNIT
This
printed
circuit
board
contains
the
receiver
circuits,
the
transmitter
exciter
stages,
the
tone
oscillator,
the
power
supply
circuits
and
the
APC
circuits.
1)
Receiver
Circuitry:
--
Input
from
the
coax
receptacle
on
the
rear
panel
is
fed
to
the
input
terminal
of
the
receiver
through
the
low
pass
filter
and
diode
switching
circuits
on
the
SW
PCB.
This
signal
is
amplified
by
Ql,
a
dual-gate
MOS-
FET.
The
local
oscillator
signal,
(127.1
-
132.095MHz)
is
applied
to
gate
2
of
92,
the
first
mixer,
with
the
output
fromthe
RF
amplifier
being
applied
to
gate
1.
The
signals
are
mixedand
results
ina16.9MHz
Ist
IF
Signal.
This
signal
passes
through
the
monolithic
crystal
filter
XF
with
a
bandwidth
of
+10KHz/3dB,
is
amplified
by
a
JFET,
Q3,
and
is
applied
to
the
base
of
the
2nd
mixer,
05.
The
base
of
05
is
also
fed
the
2nd
local
oscillator
signal
of
17.355MHz
which
is
generated
by
94.
Q5con-
verts
the
lst
IF
to
the
second
IF
of
455KHz.
Varicap
D4
is
in
the
oscillator
cir-
cuit
of
Q4
and
a
voltage
controlled
by
the
RIT
control
VR
is
applied
to
D4
via
pin
12.
The
RIT
control
varies
the
oscillator
frequency
by
approximately
+5KHZ.
The
output
of
mixer
95
is
passed
through
the
15
pole
ceramic
filter
CF
which
has
a
band-
width
of
+8KHz/6dB.
06, 7,
8,
9
&
10
are the
2nd
IF
amplifier
and
limiter
stages
from
which
the
signal
is
fed
to
the
ceramic
discriminator
CD
and
diodes
D10
and
11.
Output
from
the
discriminator
passes
through
the
de-emphasis
circuit
R43
and
C50,
the
audio
amplifier
Ql11,
and
is
fed
to
the
volume
control
via
pin
19.
The
audio
re-
turns
from
the
volume
control
via
pin
25
and
is
then
amplified
by
IC-l,
the
power
amplifier.
It
is
then
outputed
to
the
speaker
via
pin
16.
2) RF Attenuator: -- This circuit functions by lowering the bias voltage on gate
2 of the RF amplifier by operation of the swtich via pin 5 and results in again re-
duction of approximately 10dB's. It is effective in minimizing the effects of inter-
ference from strong local signals as well as squelching out weak interference, etc.
3) "S" Meter Circuit: -- The IF signal is picked off the collector of Q7, the 2nd
IF
amplifier
andis
rectified
ina
voltage
doubling
circuit
D5
and
D6
and
then
applied
to the meter to give indications of relative signal strength. VR1 adjusts meter
sensitivity and normally is set for a 20dBm signal input to give a full scale read-
ing. (Note that meter sensitivity is not linear.)
4) Squelch Circuit: -- Noise present at the discriminator is picked up through
the series and parallel tuned circuits C48-L13 and C49-L14 and is then sent to the
front panel squelch control through VR5 and pin 17. The signal is returned to the
receiver via pin 23 and is then fed to IC-2 for noise amplification. The amplified
signal is rectified in a voltage doubler circuit D12 and D13 and is then fed to the
base of the squelch switching transistor Q14. During no input conditions to the
receiver,
receiver
noises
are
rectified,
which
results
in
increasing
the
potential
of
Q14,
connecting
the
emitter
through
to
the
collector.
This
results
in
shorting
out the base of Q11 and thus grounding both the bias and the signal at this tran-
sistor which ceases to amplify and effectively cuts out the receiver noises from
being
passed
to
the
final
amplifier.
As
soon
as
an
incoming
signal
is
received
and
the receiver is quieted, the voltage on the base of Q14 drops, the connection between
its emitter and collector is broken, normal bias is applied to the base of Q1l and
-(10)-