Kurzweil K2000 - K2000 Audio;Power Board Theory - Part 12; Effects Microprocessor and Interface Theory; Effects Memory Theory

SECTION 5
AlJOPWR6. DOC 121 221 ~
5.1.6
K2000 AUDIO/POWER THEORY
SCHEMATIC PAGE 6
5.1.6.1 EFFECTS MICROCODE RAM
U50 reads its microcode instructions from a pair of 2KX8 high-speed static RAM chips, U24 (G-7)
and U25 (G-5). Actually, U50 only outputs 8 bits of microcode address; the other 3 are used to
identify 1 of 8 stored microcode routines. The SRAM is effectively dual-ported so that the
Effects Microprocessor can write into it while the LSI chip reads from it. This is necessary to
get the microcode routines loaded initially. Also for chorus and flange effects certain
locations with coefficients need to be periodically updated.
Address multiplexors U19, U20 and U22 select between addresses generated by the LSI chip when pin
1 is high and addresses generated by the Effects Microprocessor and latched in U29 and U47 when
pin 1 is low. The LSI chip indicates via RVB ENEX when it is not using the microdode RAM. Data
into and out of the microcode RAM is multiplexed on the MCD bus. For reading by the LSI chip,
the RAM's OE (Output Enable) pin is activated and its WE (Write Enable) pin deactivated. For
writing new data, the outputs of data latches U26 and U46 are enabled and the RAM's OE is
disabled and WE enabled.
5.1.6.2 EFFECTS MICROPROCESSOR
The Effects Microprocessor is responsible for loading the Microcode RAM in response to program
change messages from the Engine Board and also periodically updating coefficients for the chorus
and flanging effects. It is a 6803 which has an enhanced 6800 core with 128 bytes of RAM, one
serial port, and two parallel ports built-in. Program memory is external. Its 4MHz input clock
is derived from the 32MHz clock by divider U56 (G-6 of page 2). It is internally divided by 4
again for a 1uS memory cycle and instruction times of 2 - 10uS.
The upper 8 bits of the external address bus are latched on the 6803 and thus can be connected
directly to the external address decoder and memories. The lower B bits are multiplexed with the
data on the DA bus. Address latch U55 (E-l) latches these which are then sent to the address
decoder and RAMs. An Address Strobe signal with the correct timeing is available directly from
the 6803.
Address decoding is performed by the 3 gates (U5B & U57, F-1) and two 1-of-4 decoders (U54, F-2).
Gate U58-12 splits the 64K address space into an EPROM area of 56K (addresses $2000 - $FFFF) and
an "other" area (addresses $0000 - $1FFF). Gate U58-6 splits the "other" area into 7K of
external RAM from $0400 - $1FFF and 1K of I/O and internal RAM between $0000 and $03FF. Then the
upper decoder (U54-10) splits. out the range between $0200 and $03FF and the lower decoder splits
that 4 ways for addressing 4 output latches (U26, U29, U46, and U47; F-3 to 1-3) which interact
with the microcode RAM as described earlier.
5.1.6.3 EFFECTS MICROPROCESSOR MEMORY
Program ROM for the Effects Microprocessor is a single 64Kx8 EPROM, U48 (G-l to H-2). Much of
this space is taken by the original DSP-256 factory setups which are not used by the K2000. The
program code loaded into the EPROM is essentially what DOD supplied with a few minor patches to
skip over front panel related functions which would otherwise hang since there is not front panel
hardware. The CE pin (20) is used to activate the EPROM when addresses int he range of $2000 -
$FFFF are generated and the OE pin is used to deactivate it during all write cycles.
U51 (I-l to I-2) is a low-power static RAM chip and serves both as a scratch RAM for the
microprocessor program and as a non-volatile RAM for effects setup storage. Non-volatility is
implemented by powering U51 from BUVdd and the use of Q8 (1-2) as a fail-safe, zero power
consumption Write Enable gate. During normal operation, RESETb, which is connected to the base
of Q8 through R184, is high. Thus when the Write signal from U57-11 goes low to write, Q8
saturates and pulls its collector, which is connected to the WE pin on the RAM low. When Write
goes high or RESETb goes low, Q8 is cut off and R185 pulls the WE pin back high thus inhibiting
writing. When power off, the emitter is floating and there is no base current so R185 continues
to kee WE high with no power consumption (except leakage current).
The Engine Board software depends on the effect RAM being non-volatile. Whenever the Engine
software performs a "hard reset", such as after a battery power failure, it will reload the K2000
factory effects setups into this RAM which is a lengthy process.
5.1.6.4
INTERFACE TO EFFECTS LSI CHIP
In addition to communication through dual-port microcode RAM, the Effects Mocriprocessor communi-
cates with the Effects LSI Chip through a few dedicated control signals.
RVB GATE is a signal generated by the microprocessor that will smoothly silence any sound that
may-be reverberating in the chip and also clear the delay RAM. This is exercised whenever the
effects algorithm is changed.
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