Kurzweil K2000 - Diagnostic Test Types (v1.0); Memory Test Procedures

SECTION 4 DIAGS1_0.00c 12/13/92
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Figure 4.16 Addre •• Failure
4.20.2 Raf Teata
Since data cannot be written to ROM components, tests are done by reading the
data from the ROM components and summing the hexadecimal values of the data.
This sum is compared to a checksum stored in the last two memory addresses of
each component. The two sums must match for the test to pass.
4.20.3 I/O Teata
In an I/O test, a test data pattern is sent from the CPU to the component
being tested. The signal is processed by the component, and returned to the
central processor. If the signal returns to the central processor as
expected, the test is a success. If the observed pattern differs from the
expected pattern, the test fails.
Each of the tests described below will be either a memory test or an I/O test
(or, in some cases, a combination of the two). When performing single passes
of specific tests, the display will indicate the result of the test upon its
completion. In most cases, the result will be Success (Pass), Data Fail, or
Address Fail. Unless otherwise specified, failures will be displayed as
described in the previous paragraphs.
4.21
DESCRIPTIONS OF TESTS
4.21.1 LCD Teat
This test has both an I/O stage and a memory stage. It checks the
connections between the LCD and the engine board, as well as the memory of the
LCD itself.
The processor writes a test data pattern to the LCD memory, then reads it back
expecting a certain value. If the observed value does not match the expected
value, a data failure is indicated. This could indicate a processor error, a
faulty LCD, or a faulty connection from the LCD to the engine board.
4.21.2 Boot EPRa4 Teat
This memory test checks the integrity of the Engine software data stored in
the ROM chips located on the engine board at U3 and U6. It reads the data
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