input pin. For example, if you are using Timer1 to stop Timer0 which is outputting pulses, you must connect a jumper from Timer0
to Timer1.
Once this timer reaches the specified stop count value, and stops the adjacent timer, the timers must be reconfigured (set the
UpdateConfig bit for both timers, setting the UpdateConfig for just the output timer will restart the output in continuous mode) to
restart the adjacent timer, or the timer can be restarted by rewriting the value to the stop timer.
When the adjacent even timer is stopped, it is still enabled but just not outputting anything. Thus rather than returning to whatever
previous digital I/O state was on that terminal, it goes to the state “digital-input” (which has a 100 kΩ pull-up to 3.3 volts). That
means the best results are generally obtained if the terminal used by the adjacent even timer was initially configured as digital
input (factory default), rather than output-high or output-low. This will result in negative going pulses, so if you need positive going
pulses consider using a simple inverter IC such as the CD74ACT540E from TI.
The MSW of the read from this timer mode returns the number of edges counted, but does not increment past the stop count value.
The LSW of the read returns edges waiting for.
2.10.1.10 - System Timer Low/High Read (Modes 10 & 11)
The LabJack UE9 has a free-running internal 64-bit system timer with a frequency of 750 kHz. Timer modes 10 & 11 return the
lower or upper 32-bits of this timer. An FIO line is allocated for these modes like normal, even though they are internal readings
and do not require any external connections.
2.10.1.11 - Period Measurement (16-Bit, Modes 12 & 13)
Similar to the 32-bit edge-to-edge timing modes described above (modes 2 & 3), except that hardware capture registers are
used to record the edge times. This limits the times to 16-bit values, but is accurate to the resolution of the clock, and not subject to
any errors due to firmware processing delays.
Note that the minimum measurable period is limited by the edge rate limit discussed in Section 2.10.2.
2.10.2 - Timer Operation/Performance Notes
Note that the specified timer clock frequency is the same for all timers. That is, TimerClockBase and TimerClockDivisor are
singular values that apply to all timers. Modes 0, 1, 2, 3, 4, 7, 12, and 13, all are affected by the clock frequency, and thus the
simultaneous use of these modes has limited flexibility. This is often not an issue for modes 2 and 3 since they use 32-bit
registers.
The output timer modes (0, 1, and 7) are handled totally by hardware. Once started, no processing resources are used and other
UE9 operations do not affect the output. The major exception to this is if the TimerCounter UpdateConfig bit is set as described
earlier, as that will cause all output timers to stop and restart.
The edge-detecting timer input modes do require UE9 processing resources, as an interrupt is required to handle each edge.
Timer modes 2, 3, 5, 9, 12, and 13 must process every applicable edge (rising or falling). Timer modes 4 and 8 must process
every edge (rising and falling). To avoid missing counts, keep the total number of processed edges (all timers) less than 100,000
per second. That means that in the case of a single timer, there should be no more than 1 edge per 10 μs. For multiple timers, all
can process an edge simultaneously, but if for instance 6 timers get an edge at the same time, 60 μs should be allowed before any
further edges are applied. If streaming is occurring at the same time, the maximum edge rate will be less (25,000 per second),
and since each edge requires processing time the sustainable stream rates can also be reduced.
2.11 - SCL and SDA (or SCA)
Reserved for factory use. Note that the I²C functionality of the UE9 does not use these terminals.
2.12 - DB37
The DB37 connector brings out analog inputs, analog outputs, FIO, and other signals. Some signals appear on both the DB37
connector and screw terminals, so care must be taken to avoid a short circuit.
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