LG 24MT48DF - Block Diagram

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LGE Internal Use Only
Copyright © LG Electronics. Inc. All right reserved.
Only for training and service purposes
BLOCK DIAGRAM
MSTAR M1A+
COMPONENT
RGB
HDMI1
DSUB R/G/B/H/V
Audio IN
HP L & R out
COMP_Y , Pb ,Pr
COMP_L & R_IN
USB (Jpeg,MP3,DVIX)
LGIT Half NIM (DVB T/C)
SCART (Full)
PCMCIA Slot
FE_Tuner_SDA&SCL
SCART_OUT
FE_TS_CLK FE_TS_VAL_ERR FE_TS_SYNC FE_TS_DATA[0~7]
NAND Flash
TC74LCX244FT Buffer
CI_CLK CI_VIAL Error CI_SYNC CI_DATA[0~7]
CI ADDR[0~7]
PCM_DATA [0~7]
PCM_A
[0~7]
CI_ADDR[0~14] REG CI_OE CI_IORD CI_IOWR CI-WE
PCM_A
[0~14]
FE_DE _SDA&SCL
SERIAL Flash
CVBS
TV L&R Sound
F_RB PF-OE
PF_CEO
SPI_CK SPI_CI SPI_CS SPI_DO
System EEPROM
EEPROM SCL & SDA
Panel
Digital amp (BM28720MUV)
SP (L)
SP (R)
Audio_ Master_CLK /DATA[3]
LVDS
SIF
HP L/R
H/P
Country Option (DVB only)
AMP SCL&SDA
CVBS
XTAL : 24MHz
TMDS : 148.5MHz
Country Option
Country Option (DVB only)
HDMI2
HDMI_TMDS & HDMI I2C
HDMI_TMDS & HDMI I2C
SCART R/G/B/H/V
-DVB-T/C : TDJS-G301D (Half NIM)
-DVB-T2/C/S2 : TDJA-G301D (Combo Half NIM)
*Tuner country Option
*H/P, Audio IN, DSUB, COMPONENT Option
- MT58 Use - MT48 Not use
*HDMI Option MT58 2EA Use MT48 1EA use
*
Internal DDR3: 800MHz