LG 32LG6000 - Block Diagram

Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
- 20 -
BLOCK DIAGRAM
1. A TN Main Overall
TS[0:7]
CVBS, L/R
DDR2 SDRAM
(64MByte)
HYNIX
IC700
NAND Flash
HYNIX
IC404
LVDS TMDS ODD[10 bit]
SPDIF_OUT
Digital amp
(NTP3000A)
IC600
RS-232C
TMDS351PAG
IC200
YPbPr L/R
RGB, CVBS
CVBS
DTV/MNT OUT
I2S
24LC512
512Kbit
IC901
RGB,PC L/R
Tuner
(TDFV-G135D1)
TU300
TMDS[0:7]
74LVC541A(PW)
Buffer
IC400
CI Slot
(P400)
74LVC245A
Bi-Buffer
IC402
DATA[0:7]
74LCX244MTC
Buffer
IC403,405,406
Address[0:14] ,CTRL signals
TMDS[0:7]
CVBS
Tuner V out
NLASB3157
IC500
LVDS TMDS EVN[10 bit] LVDS TMDS ODD[10 bit]
Host Address[1:16]
Host Data[0:15]
LPF
DDR2 Data[0:15]
DDR2 SDRAM
(64MByte)
HYNIX
IC701
DDR2 Data[16:31]
DDR2 Address[0:12]
MICOM
WT61P8
IC802
MAX3232CDR
IC104
NLASB3157
IC101
AT24C16AN
16K
IC801
MSP4458G
IC603
SIF,SCART1,2 L/R,AM Audio Switching LR
I2S
TV out, DTV out LR
TPS2042DBRG4
USB Power
IC902
USB Power 500mA
FLI10620H