LG 32LN5300-UB - Block Diagram

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LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BLOCK DIAGRAM
SPDIF
Component
HDMI
D_IF
M1
SERIAL FLASH
MXIC 8MB(64Mb)
MX25L6406EMI
LVDS
(FHD/HD 60z)
USB2.0
DP/D M
SPK L/R
X-tal
24MHz
FPC(51P/FHD)
I2S
SPDIF
L/R
Y/Pb/Pr, L/R
Rear
TMDS
DDR3 Add. DDR3 Data
SPI
AV
Side
TMDS
HDMI MHL
CVBS, L/R
CONTROL
IR & LED
KEY1
IR
LED_R
I2C
RS-232C
FPC(30P/HD)
MAX3232
RS232C
CLK 667MHz
Internal
Micom
(PM)
I2C
DDR3 128MB(1Gb)
Hynic
H5TQ1G63DFR
AT24C512C-SSHD-T
512k bit
Half NIM
(SI2158_ATSC_1INPUT)
A_IF
AMP
STA380BWE
(CLK 800MHz)