LG 47LW570Y - Page 50

Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
3D_SYNC_OUT
80P mini-LVDS Output
RIGHT
80P mini-LVDS Output
LEFT
DDR3 SDRAM
-
1Gbit (x16)
- 800MHz
DDR3 SDRAM
-
1Gbit (x16)
- 800MHz
DDR1_DATA[15:0]
DDR1_A[12:0]/
BA[2:0]/CLK/CKE
DDR0_DATA[15:0]
DDR0_A[12:0]/
BA[2:0]/CLK/CKE
Vol. Regulator
(TPS51200)
Vol. Regulator
(TPS51200)
+1.5V1
+0.75V_VTT1
Vol. Regulator
(TPS51200)
Vol. Regulator
(TPS51200)
+1.5V0
+0.75V_VTT0
SPI_DO/CK/CS
SPI_DI
SPI FLASH
(4Mbit)
SPI FLASH
(4Mbit)
I2C_SDA
I2C_SCL
VCOMLOUT/
VCOMROUT
P_VCOM/
VCOMLFB/
VCOMRFB
DPM/FLK
PMIC
(TPS65168)
(0x42)
PMIC
(TPS65168)
(0x42)
VCC_LCM/VDD_LCM/
VGH/VGL/HVDD/VCORE
VLCD_POWER
+1.0V
DC-DC Converter
(AOZ1024DI)
DC-DC Converter
(AOZ1024DI)
VLCD_POWER
+3.3VD
DC-DC Converter
(AOZ1072AI)
DC-DC Converter
(AOZ1072AI)
VLCD_POWER
+2.5V
+3.3VD
LDO Regulator
(AP2132MP)
LDO Regulator
(AP2132MP)
Z_OUT
I2C_SDA
I2C_SCL
VCC_LCM/VDD_LCM/
HVDD
P-GAMMA
IC
(MAX9668B)
(0xE8)
P-GAMMA
IC
(MAX9668B)
(0xE8)
GMA[18:15],
GMA[9:5]
P_VCOM
DDR3 SDRAM
-
1Gbit (x16)
- 800MHz
DDR3 SDRAM
-
1Gbit (x16)
- 800MHz
LG1121
(0x1C, direct
0xB2, in-direct)
XTAL_IN
XTAL_OUT
X-Tal
(24.75Mhz)
FRC_RESET
XTR
T-Con
(0x72)
I2C_SDA
I2C_SCL
I2C_TCON_SDA
I2C_TCON_SCL
EEPROM
(64kbit)
EEPROM
(64kbit)
Octa-link LVDS
VLCD_POWER
(+12V)
FRC_RESET
I2C_SDA
I2C_SCL
3D_SYNC_OUT
R_VS, M2_SCLK/MOSI
I2C_SDA
I2C_SCL
2Dto3D
(0x8E)
+3.3VD
+1.5V0
DC-DC Converter
(AOZ1072AI)
DC-DC Converter
(AOZ1072AI)
+3.3VD
+1.5V1
DC-DC Converter
(AOZ1072AI)
DC-DC Converter
(AOZ1072AI)
I2C_SDA
I2C_SCL
VCC_LCM/VDD_LCM/
HVDD
P-GAMMA
IC
(MAX9668B)
(0xEA)
P-GAMMA
IC
(MAX9668B)
(0xEA)
GMA[14:10],
GMA[4:1]
Dual-link HF mini-LVDS
(@297MHz)
Dual-link HF mini-LVDS
(@297MHz)
Dual-link LVDS(@74.25MHz)
51Pin LVDS Input
+1.0VD
DC-DC Converter
(AOZ1072AI)
DC-DC Converter
(AOZ1072AI)
VLCD_POWER
GP3 Backend block diagram (SG)