LG 47LW570Y - Block Diagram

Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
5. Block Diagram
[VI_SC_R1],[VI_SC_G1],[VI_SC_B1]
BCM35230
[COMP1_DET]
[COMP1_Y]
[COMP1_Pb]
[COMP1_Pr]
DSUB_R / G / B
PC L,R
EDID EEPROM
AT24C02BN-10SU-1.8
RGB DET
[DSUB_R+/G+/B+]
DSUB_ V / HSYNC
[DSUB_V/H SYNC]
[DSUB_DET] // GPIO
[EDID_WP] MICOM
[RGB_DDC_SCL]
[RGB_DDC_SDA]
RGB_DDC_SCL
RGB_DDC_SDA
[PC_L_IN]
[PC_R_IN]
[SPDIF_OUT]
SPDIF
R
L
CVBS
AV DET
[AV1_R_IN]
[AV1_L_IN]
[AV1_CVBS_IN]
[AV1_CVBS_DET]
COMP_Y
COMP_PB
COMP_PR
COMP DET
COMP1
R
L
CVBS
AV DET
[AV1_R_IN]
[AV1_L_IN]
[AV1_CVBS_IN]
[AV1_CVBS_DET]
AV1
AV2
COMP2_R/G/B
[BSC_S_SCL]
[BSC_S_SDA]
HDMI1
HDMI2
HDMI3
HDMI4
HDMI
HUB IC
[HDMI0_-/+]
Jack Interface