SPLT_DCLK
SPLT_ASDO
+2.5V_FPGA
SPLT_SYSCLK
SPLT_CSO
SPLT_DATAO
+2.5V_FPGA
SPLT_MSEL[2]
22
AR701
SPLT_MSEL[1]
SPLT_MSEL[3]
SPLT_MSEL[0]
+2.5V_FPGA
2SC3052
Q703
E
B
C
SPLT_RESET2V5
+3.3V
2SC3052
Q702
E
B
C
SPLT_SCL
SPLT_SDA
+2.5V_FPGA
SPLT_SDA2V5
I2C_SDA_S
+3.3V
+2.5V_FPGA
+3.3V
SPLT_SCL2V5
I2C_SCL_S
+3.3V
SPLT_TP[6]
SPLT_TP[0]
SPLT_TP[5]
SPLT_TP[4]
EPCS4SI8N
IC701
3
VCC
2
DATA
4
GND
1
NCS
5
ASDI
6
DCLK
7
VCC_1
8
VCC_2
SAM2333
LD700
A2[RD]
C
A1[GN]
SPLT_LED[0]
SPLT_STATUS
SPLT_CE
SPLT_CONFIG_DONE
SPLT_CONFIG
+2.5V_FPGA
JTP-1127WEM
SW700
12
43
+3.3V
LG1122_RST
0.1uF
16V
C743
0.1uF
16V
C711
+2.5V_FPGA_VCCA_SPLT
0.1uF
16V
C721
0.1uF
16V
C765
0.1uF
16V
C747
0.1uF
16V
C746
0.1uF
16V
C710
+1.2V_FPGA
0.1uF
16V
C769
0.1uF
16V
C729
0.1uF
16V
C744
0.1uF
16V
C768
0.1uF
16V
C713
0.1uF
16V
C707
0.1uF
16V
C767
0.1uF
16V
C735
0.1uF
16V
C750
+2.5V_FPGA
0.1uF
16V
C709
BLM18SG700TN1D
L704
0.1uF
16V
C777
0.1uF
16V
C731
0.1uF
16V
C748
0.1uF
16V
C774
0.1uF
16V
C771
0.1uF
16V
C733
0.1uF
16V
C738
+1.2V_FPGA
0.1uF
16V
C756
0.1uF
16V
C773
0.1uF
16V
C737
0.1uF
16V
C736
0.1uF
16V
C754
0.1uF
16V
C779
0.1uF
16V
C772
0.1uF
16V
C722
0.1uF
16V
C742
+2.5V_FPGA_VCCA_SPLT
0.1uF
16V
C726
0.1uF
16V
C749
0.1uF
16V
C762
0.1uF
16V
C725
0.1uF
16V
C740
0.1uF
16V
C759
0.1uF
16V
C766
+1.2V_FPGA_VCCD_SPLT
0.1uF
16V
C723
0.1uF
16V
C734
0.1uF
16V
C755
+1.2V_FPGA
0.1uF
16V
C751
0.1uF
16V
C752
0.1uF
16V
C724
0.1uF
16V
C732
BLM18SG700TN1D
L703
+2.5V_FPGA
0.1uF
16V
C753
0.1uF
16V
C758
0.1uF
16V
C727
0.1uF
16V
C730
0.1uF
16V
C764
0.1uF
16V
C763
0.1uF
16V
C776
0.1uF
16V
C717
0.1uF
16V
C728
0.1uF
16V
C760
+2.5V_FPGA_VCCA_SPLT
0.1uF
16V
C739
0.1uF
16V
C778
0.1uF
16V
C720
+1.2V_FPGA_VCCD_SPLT
0.1uF
16V
C757
+2.5V_FPGA
0.1uF
16V
C745
0.1uF
16V
C712
0.1uF
16V
C718
0.1uF
16V
C761
0.1uF
16V
C741
0.1uF
16V
C770
+1.2V_FPGA_VCCD_SPLT
0.1uF
16V
C719
0.1uF
16V
C775
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPLT_SCL
SPLT_SDA
33
R720
33
R730
L700
OPT
+3.3V
0
R734
OPT
22 R706
22 R705
22 R707
22 R701
22
R738
22
R758
22
R759
22
R743
22
R736
22
R711
22
R712
4.7K
R735
4.7K
R715
OPT
4.7K
R713
OPT
4.7K
R716
4.7K
R717
4.7K
R724
1K
R737
1K
R748
1K
R714
2K
R718
2K
R719
5.6K
R723
5.6K
R722
33
R733
33
R725
10K
R729
10K
R732
10K
R731
10K
R745
10K
R747
10K
R746
27
R744
330
R700
0
R726
0
R727
BLM18PG121SN1D
L702
0.1uF
16V
C704
0.1uF
16V
C703
0.1uF
16V
C702
100pF
50V
C708
10pF
C715
0.1uF
16V
C706
18pF
50V
OPT
C701
18pF
50V
OPT
C700
0
OPT
R762
0
R766
0
OPT
R760
0
R764
0
OPT
R765
0
OPT
R767
0
R763
0
R761
+2.7V_FPGA
APX803D29
IC700
1
GND
3
VCC
2
RESET
12507WR-04L
P700
1
2
3
4
5
1K
R755
12507WR-10L
P701
1
2
3
4
5
6
7
8
9
10
11
SPLT_TMS
1K
R753
22
R751
0.1uF
C716
1K
R754
22
R750
22
R752
FMTB_TDO
22
R749
SPLT_TDI
+2.5V_FPGA
SPLT_TCK
MDS62110215
M701
GASKET_SPLT
MDS62110215
M702
GASKET_SPLT
MDS62110215
M703
GASKET_SPLT
10K
R721
OPT
12.288MHz
X700
4
VCC
1
ST
2
GND
3
OUT
0
R728
EP4CE15F23I7N
IC600
GND_1
L10
GND_2
L11
GND_3
M10
GND_4
M11
GND_5
L12
GND_6
L13
GND_7
M12
GND_8
M13
GND_9
N11
GND_10
K11
GND_11
N12
GND_12
K12
GND_13
K13
GND_14
N13
GND_15
N10
GND_16
K10
GND_17
J9
GND_18
D7
GND_19
J5
GND_20
H8
GND_21
A1
GND_22
C5
GND_23
C9
GND_24
C11
GND_25
C12
GND_26
C14
GND_27
C16
GND_28
A22
GND_29
E20
GND_30
G20
GND_31
L20
GND_32
P19
GND_33
V20
GND_34
Y20
GND_35
AB22
GND_36
Y18
GND_37
Y16
GND_38
Y12
GND_39
Y11
GND_40
Y9
GND_41
Y5
GND_42
AB1
GND_43
N3
GND_44
U3
GND_45
W3
GND_46
D3
GND_47
F3
GND_48
K3
GND_49
G2
GND_50
AA2
GND_51
AA22
GND_52
H3
GND_53
R3
GND_54
AB6
GND_55
Y15
GND_56
T20
GND_57
J19
GND_58
C18
GND_59
D8
GNDA1
U5
GNDA2
E18
GNDA3
F5
GNDA4
V18
VCCINT_1
J11
VCCINT_2
J12
VCCINT_3
L14
VCCINT_4
M14
VCCINT_5
P11
VCCINT_6
P12
VCCINT_7
L9
VCCINT_8
M9
VCCINT_9
J13
VCCINT_10
J14
VCCINT_11
K14
VCCINT_12
J10
VCCINT_13
K9
VCCINT_14
N9
VCCINT_15
P9
VCCINT_16
P10
VCCINT_17
P13
VCCINT_18
U16
VCCINT_19
U17
VCCINT_20
T13
VCCINT_21
J8
VCCIO1_1
D4
VCCIO1_2
F4
VCCIO1_3
K4
VCCIO1_4
H4
VCCIO2_1
N4
VCCIO2_2
U4
VCCIO2_3
W4
VCCIO2_4
R4
VCCIO3_1
AB2
VCCIO3_2
W5
VCCIO3_3
W9
VCCIO3_4
W11
VCCIO3_5
AA6
VCCIO4_1
AB21
VCCIO4_2
W12
VCCIO4_3
W16
VCCIO4_4
W18
VCCIO4_5
Y14
VCCIO5_1
P18
VCCIO5_2
V19
VCCIO5_3
Y19
VCCIO5_4
T19
VCCIO6_1
E19
VCCIO6_2
G19
VCCIO6_3
L19
VCCIO6_4
J20
VCCIO7_1
A21
VCCIO7_2
D12
VCCIO7_3
D14
VCCIO7_4
D16
VCCIO7_5
D18
VCCIO8_1
A2
VCCIO8_2
D5
VCCIO8_3
D9
VCCIO8_4
D11
VCCIO8_5
E8
VCCA1
T6
VCCA2
F18
VCCA3
G6
VCCA4
U18
VCCD_PLL1
U6
VCCD_PLL2
E17
VCCD_PLL3
F6
VCCD_PLL4
V17
AO3438
Q700
G
D
S
AO3438
Q701
G
D
S
7 23
25Ohm
FPGA Reset Level Shifter (3.3V to 2.5V)
SCL
FPGA I2C Level Shift (3.3V <-> 2.5V)
5V
SDA
GND
LED
SPLT PWR
FPGA CONFIGURATION
Oscillator for System Clk
TP
2012.06.05EAX64768002
Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
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