LG Flatron 795FT Plus (FB795E-UA) - Pin Configuration

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PIN CONFIGURATION
M24C08 Serial I
2
C BUS EEPROM
SYMBOL
E0-E2
SDA
SCL
WC
Vcc
Vss
DESCRIPTION
Chip Enable Input
Serial Data Address Input/Output
Serial Clock
Write Control
Supply Voltage
Ground
1
PSDIP8 (BN)
0.25mm Frame
8
1
1
SO8 (MN)
150mil Width
TSSOP8 (DW)
169mil Width
8
8
Logic Dirgram
1
2
3
4
Q
1
Q1
CP1
CD1
5
6
7
D
1
SD1
VSS
HEF4013B
14
13
12
11
V
DD
Q2
Q2
CP2
10
9
8
C
D2
D2
SD2
Pin Configuration
SYMBOL
Q1
Q1
CP1
CD1
D1
SD1
VSS
SD2
D2
CD2
CP2
Q2
Q2
VDD
DESCRIPTION
True Output 1
Complement Output 1
Clock Input 1 (L
→H Edge-Triggered)
Asynchronous Clear Direct Input 1 (Active HIGH)
Data Input 1
Asynchronous Set Direct Input 1 (Active HIGH)
Ground
Asynchronous Set Direct Input 2 (Active HIGH)
Data Input 2
Asynchronous Clear Direct Input 2 (Active HIGH)
Clock Input 2 (L→H Edge-Triggered)
Complement Output 2
True Output 2
12V DC Supply
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
14
HEF4013B Dual D Flip-Flop
S
D
C
D
CP
D
Q
Q
S
D
C
D
CP
D
Q
Q
V
DD
= Pin 14
V
SS
= Pin 7
1
6
5
3
4
8
9
11
10
2
13
12
BLOCK DIAGRAM