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LGE Internal Use Only Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. Technical brief
F. System Control Subsystem
The SYSCON resides at the top level of the circuit architecture and is responsible for clock
generation and clock and reset distribution within the digital baseband controller, as well as to
external devices.
The block is a slave peripheral under control of the ARM processor. The programming of the
SYSCON controls the fundamental modes of operation within the digital baseband controller.
Individual blocks can also be reset and their clocks held inactive by accessing the appropriate
control registers.
3.1.4 RF Interface
A. GSM Radio Link Interface
DB3150 controls GSM RF part using these signals through GSM RF chip-RF3000.
y RF_DATA_A
y RF_DATA_B
y RF_DATA_C
y RF_DATA_STRB
Figure 3-1-5. Schematic of GSM RF Interface
B. WCDMA Radio Link Interface
y RF_WCDMA_PA_0_EN
y RF_WCDMA_PA_1_EN
y RF_WCDMA_DCDC_EN
y RF_WCDMA_PWRDET_EN
Figure 3-1-6. Schematic of WCDMA RF Interface
Y2
Y3
AA2
Y4
RF_DATA_A
RF_DATA_B
RF_DATA_C
RF_DATA_STRB
DCLK_DATSTR
AMP_LSB_FREQ_LSB
IDATA_FREQ_MSB
QDATA_AMP_MSB
AB7
Y7
W7
W8
Y8
Y9
W9
W10
Y10
AB6
AB5
V7
AB8
Y2
Y3
AA2
Y4
RF_DATA_A
RF_DATA_B
RF_DATA_C
RF_DATA_STRB
RF_WCDMA_PA_0_EN
RF_WCDMA_PA_1_EN
RF_WCDMA_DCDC_EN
RF_WCDMA_PWRDET_EN
ADC_I_NEG
ADC_I_POS
ADC_Q_NEG
ADC_Q_POS
DAC_I_NEG
DAC_I_POS
DAC_Q_NEG
DAC_Q_POS
TX_POW
WTX_BAND_1_EN
WPOW_DET_EN
WPOW_DET
WDCDC_EN
WRX_I_P
WRX_I_N
WRX_Q_P
WRX_Q_N
WTX_Q_N
WTX_Q_P
WTX_I_N
WTX_I_P
DCLK_DATSTR
AMP_LSB_FREQ_LSB
IDATA_FREQ_MSB
QDATA_AMP_MSB
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