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LGE Internal Use Only Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. Technical brief
C. Synthesizer
The RX and TX RF VCOs are fully integrated and self-calibrated on manufacturing tolerances.
They have 16 different frequency ranges that are selected internally depending on the frequency
programming. The calibration is done on each low to high logical transition of the SYNON bit in the
control register or on each change of the integer divider ratio of the RF fractional N synthesizer.
A high-performance RF fractional-N synthesizer PLL is included on-chip which enables the
frequency of the RF VCO to be synthesized. The frequency is set through the 3-wire serial
programming bus. The PLL is based on Sigma-Delta (î .) fractional-N synthesis that enables the
required channel frequency, including Automatic Frequency Control (AFC) from a free running
external 26 MHz reference frequency. Very low close-in-phase noise is achieved. This allows
widening of the PLL loop bandwidth and shorter settling time. The programmable main dividers
are controlled by a second order î -modulus controller. They divide the RF VCO signals down to
frequencies of 26 MHz (12 Hz step programmability). Their phase is then compared in a digital
Phase/Frequency Detector (PFD) to the 26 MHz reference clock signal.
The phase error information is fed back to the RF VCO through the charge pump circuit
that .sources. into or .sinks. current from the loop filter capacitor, thus changing the VCO
frequency such that the loop finally gets phase-locked.
1
01C
p
65
2
0
1
C
I
ND
0603
701C
p
2
2
p2
2
8
01C
30
6
0
5.6n
L104
p
2
2
1
1
1C
0603
022
2
01R
3
0
60
3060
02
2
301R
I
ND
7
31
C
8V2_ADAR
V
p65
811C
2.4n
L105
8V2
_
A
D
A
R
V
0603
8
2
1
C
p01
30
6
0
p
0
1
621
C
02
2
6
0
1
R
3
0
6
0
0
22
7
0
1
R
3060
8
V
2
_
A
D
A
R
V
8V2_ADA
R
V
p
2
.
883
1
C
I
ND
9
31
C
8
V
1
_D
ARG
I
D
V
0
0F0
A
F
4
1G
2
B
E
FA
S
2
0
1
L
F
45
1
32
G1 O1
IN
G2 O2
0
0F
0
AK59
G1B
EF
A
S
3
0
1LF
25
1
4
3
3G
NI
TU
O
1
G2G
60
1
U
N
H5916MO_00
1
3FR
20
19
18
17
16
15
14
13
12
11
1
2
0
1
2
2
9
3
28
4
27
526
625
724
823
9
22
031
31
32
33
34
35
36
37
38
39
40
41
PGND
VCCTX
RF_DAC2
RF_DAC1
NC13
MIX1_B
MIX1_A
NC12
NC11
NC10
VCCRX
XTD
N
G
9C
N
1C
NT
UO_
1
AN
L
2C
N
8
C
N
1_
XT
NI_
1ANL
3
C
N7
C
N
XT
O
LCC
V6
CN
AIX
T
XROLC
C
V
BIX
T
5
C
N
AQXT
D
DV
B
Q
X
TT
ST
VGACT L
DATA
CLK
EN
REFIN
NC4
RXIA
RXIB
RXQA
RXQB
7
5
1
C
p6
5
1_
D
N
A
B_XR
W
P
_
I
_
X
RW
N
_
I
_
X
RW
P_
Q
_
X
RW
N_
Q
_
X
RW
1_
D
N
A
B_
D
O
MX
T
W
N
_Q
_
X
T
W
P
_
Q
_
XTW
N
_
I
_
X
T
W
P_I_XTW
C
CV_A
P
W
SA
I
B_APW
K
L
CW
BR
T
S
_
L
R
TC
_
FR
A
T
A
D
_
L
R
T
C
_
FR
K
LC_
L
R
T
C
_
F
R
3
06
0
3
06
0
Figure 3-7-4. WCDMA Transceiver schematic
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