LG GS290 - Memory

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Copyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3. TECHNICAL BRIEF
GS290 Operational Description Revision B
LG Electronics 40/136 LGE Property
3.6. Memory
2Gbit NAND & 1Gbit DDRSDRAM employed on GS290 with 8 & 16 bit parallel data bus thru ADD(0) ~ ADD(29).
The 512Mbit Nand Flash memory with DDRAM stacked device family offers multiple high-performance
solutions.
Figure 9 Flash memory & DDR RAM MCP circuit diagram
n
0
15
31
C
041C n
0
1
n01441C
641C n01
K3.3501R
TP103
u1.0911C
SD_1V8
401R K01
u1.0901C
921C u1.0
SD_1V8
SD_1V8
TP106
TP108
TP109
TP112
TP104
8
1
1C n0
1
u1.0141C
541C u1.0 631C u1.0
n01731C
K522H1HACB-B060
U101
21T
11T
01T
3T
2T 1T
2
1R
11R 01R
3R
2R
1R
21P
1
1P
3P 2P 1P 2N
2M 2L
01K 9K 8K
5K 4K 2K
1
1J
01J 9J 8J 7J
6J 5J 4J
3J
P8D5
P4D6
E6
P6F6
C8F5
C4E5
D7
P5C7
C6
P9L7
P7L6
H10K7
G2K6
C9N9
C5M9
L9
H2N8
M8
N3L8
E3N7
K3M7
L3N6
F3M6
M3N5
G3M5
L5
D11N4
E11M4
F11L4
G11E9
K11E7
L11F7
M11G5
N11G7
C10D9
D10D8
E10E8
F10F8
L10G8
M10G4
N10F4
P10E4
D4
2J
9
H
8H 7H 6H 5
H
4
H
3H
01G
9G 6G
9F
2F
11
H
2E
3D
2D 1
D
2
1
C
1
1
C
3C 2
C
1
C
2
1B
11B 01B
3B 2B 1B
21A
11A
0
1A 3A
2A
1A
1CN 2CN 3
C
N
4CN
5CN
6CN
7CN
8CN
9CN
01CN 11CN 2
1
C
N
3
1
C
N
41CN
51CN
61CN
7
1
C
N
81CN 91CN 0
2
C
N
1
2
C
N
22CN
32
C
N
4
2
C
N
5
2
C
N
62CN 72CN 8
2
C
N
92CN 0
3
C
N
13CN
23CN
33
C
N
43
C
N
53CN
A0
A1 I_O0
A2 I_O1
A3 I_O2
A4 I_O3
A5 I_O4
A6 I_O5
A7 I_O6
A8 I_O7
A9 I_O8
A10 I_O9
A11 I_O10
A12 I_O11
A13 I_O12
DQ0 I_O13
DQ1 I_O14
DQ2 I_O15
DQ3
DQ4 _CE
DQ5 _WEN
DQ6 _RE
DQ7 ALE
DQ8 CLE
DQ9 R__B
DQ10 _WP
DQ11
DQ12 VCCN1
DQ13
DQ14 VSS1
DQ15 VSS2
LDQM VSS3
UDQM VSS4
LDQS VSS5
UDQS VSS6
_CLK
CLK VSSQ
CKE
BA0 VDD1
BA1 VDD2
_RAS VDD3
_CAS
_WED VDDQ1
_CS VDDQ2
63CN 73CN 8
3
C
N
93CN
04CN 14CN
24CN
3
4
C
N
44CN
54CN 64CN 7
4
C
N
84
C
N
94CN 05CN 15CN
25
C
N
35CN 45CN 5
5
C
N
65
C
N
75CN 85
C
N
9
5
C
N
06
C
N
16CN 26CN 3
6
C
N
46CN 56
C
N
66CN
76CN
8
6
C
N
96
C
N
07CN
TP102
TP107
ADD[29]
DATA[10]
DATA[15]
DATA[13]
DATA[12]
DATA[11]
DATA[9]
DATA[8]
DATA[2]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[1]
DATA[0]
UDQS
LDQS
ADD[28]
ADD[27]
ADD[26]
SDCLKI
_WR
_WR
SDCLKO
_RD
_RAM_CS
CKE
_CAS
FCDP
_BC1
_BC0
_NAND_CS
ADD[25]
ADD[4]
ADD[3]
ADD[24]
ADD[23]
ADD[22]
ADD[21]
ADD[20]
ADD[2]
ADD[19]
ADD[18]
ADD[17]
ADD[17]
ADD[16]
ADD[16]
ADD[9]
ADD[8]
ADD[13]
ADD[7]
ADD[12]
ADD[6]
ADD[11]
ADD[5]
ADD[10]
ADD[1]
ADD[0]
_RAS
ADD[15]
ADD[14]
DATA[14]
BA0
BA1
_WP
ADD[16:29]
A
DD[0:15]
DATA[0:15]
(2048Mbit NAND / 1024 Mbit DDR SDRAM, 1.8V I/O)
Large Block Memory
GS290 Operational Description Revision B
LG Electronics 40/136 LGE Property
3.6. Memory
2Gbit NAND & 1Gbit DDRSDRAM employed on GS290 with 8 & 16 bit parallel data bus thru ADD(0) ~ ADD(29).
The 512Mbit Nand Flash memory with DDRAM stacked device family offers multiple high-performance
solutions.
Figure 9 Flash memory & DDR RAM MCP circuit diagram