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LGE Internal Use Only Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. Technical Brief
3. Common
* WLAN_REG_ON : If low the internal regulators will be disabled.
* SLEEP_CLK : LPO clock (32.768kHz) input. Used for low-power mode timing.
* CLK_IN : Crystal amplifier input or frequency reference input.
* CLK_REQ : Crystal Circuit / Reference Clock Enable (active-high)
Figure. Block Diagram of WiFi Interface
Figure. Block Diagram of BT Interface
GPIO 35
GPIO 21
GPIO 94
WLAN_CMD
WLAN_CLK
WLAN_SDIO[3:0]
WLAN_RESET_N
REG_ON
WLAN_HOST_ WAKEUP
MSM7200A
VDD_TCXO
26MHz
RP 103K281D-TR -F
CE
CLK_IN
CLK_REQ
VOUT
SLEEP_CLK
PM7540
32. 768 k Hz
+V PW R
VREG_MSMP_2.6V
WLAN_BT_IN_OUT
LBEH 19UNBC
VDD_TCXO
26MHz
RP 103K281D-TR -F
CE
CLK_IN
CLK_REQ
VOUT
SLEEP_CLK
GPIO 21
REG_ON
MSM7200A
PM7540
32. 768 k Hz
+VPWR
VREG_MSMP_2 .6 V
BT_UART_RXD
BT_UART_TXD
BT_UART_RTS
BT_UART_CTS
BT_PCM_CLK
BT_PCM_DIN
BT_PCM_SYNC
BT_PCM_DOUT
BT_WAKEUP
BT_HOST_WAKEUP
BT_RESET_N
GPIO 92
GPIO 83
GPIO 93
AUX_PCM
High speed UART
WLAN_BT_IN_OUT
LBEH 19UNBC