3. TECHNICAL BRIEF
Interfaces
The base band is connected via a DigRF V3.09 high speed data interface with a maximum clock frequency of 312
MHz. The pure digital interface enables the digital baseband to shrink efficiently, as all the analog functionality is
within the RFIC. All data and control traffic is multiplexed via the RX and TX interface lines. The IC features a high
level programming model enabling the complete compressed mode operation of the device in an RF engine
environment.It handles RX and TX power control, also incorporating the calibration data. The complete timing is
optimized for compressed mode operation of the transceiver, it controls the front end components of the
engine (PA´s, switches, LNA´s). Additionally a SPI control bus for front end component control is available in the
IC, which also enables the readback of data from external components, thus the handling of functions like PA
saturation, mismatch detection, overheating (incorporated in the closed loop power control) can be adopted.
AFC Control
The AFC control is maintained by providing a voltage generated by a 12-Bit DAC to the external TCVCXO module,
which means the reference clock is synchronized to the system frequency.
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