3. TECHNICAL BRIEF
• SB_uC: including
– The 3G modem controller subsystem including the AHB_3G_SYS bus, and master interfaces to three
peripheral buses 3G_MEMIF, AHB1_3G_L1 and AHB2_3G_L1
– The USIF trace interface
– The Mtrace trace interface to the MIPI port
– The interrupt control unit ICU
–An AHB2AHB bridge connecting the 3G modem controller to the 3G_Master interface via AHB_3G_SYS
• SB_TXSR: including
– The UMTS cell searcher (SRCH) HW peripheral
– The UMTS delay profile estimator (DPE) HW peripheral
– The measurement RAM (MRAM) buffering the results of both SRCH and DPE
– Access from the 3G modem controller subsystem to MRAM via the 3G_MEMIF bus
– Transmit modulator (TxMod) and transmit bit processor (E-TxBitProc) HW peripherals performing transport
channel multiplexing, channel coding and modulation for all uplink data streams. These blocks exchange
data via a dedicated RAM SBRAM-TX
– Access to the transport blocks stored in the COMRAM by the E-TxBitProc via the dedicated bus system
– Configuration access from the 3G modem controller subsystem via the AHB_3G_L1 AHB bus
• SB_RAKE: including
– The DSP subsystem performing sub-slot signal processing and control for the Rake and HSDPA-IRX peripherals.
The DSP subsystem is connected to the 3G modem controller via shared memory and interprocess
communication via comunication flags, and to the Rake and HSDPA-IRX peripherals via a dedicated bus
– The Rake inner receiver HW peripheral performing demodulation of all UMTS and HSUPA physical channels
– Configuration Access from the 3G modem controller subsystem via the AHB_3G_L1 AHB bus
– Access to the SBRAM1 performing framewise storage of the demodulated coded composite transport channels
via the dedicated bus system
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