LG LG-P970 - Page 72

3. TECHNICAL BRIEF
- 72 -
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LGE Internal Use Only
PR
ELIM
INA
RY
L4
Display
subsystem
MPU
subsystem
SGX
IVA2.2
subsystem
sDMA
Camera
ISP
USB
HS-HOST
D2D
DAP
OCM
ROM
SMS:
SDRAM
memory
scheduler /
rotation
SDRC: SDRAM
memory
controller
GPMC: general-
purpose memory
controller
L4 interconnect (peripheral)
UART3, UART4, McBSP2, McBSP3, McBSP4,
WDT3, GPTIMER2, GPTIMER3,
GPTIMER4,GPTIMER5, GPTIMER6,
GPTIMER7, GPTIMER8, GPTIMER9, GPIO2,
GPIO3, GPIO4, GPIO5, GPIO6
L4 interconnect (core)
SCM, CM, display SS, sDMA, USB TLL,
HS USB Host, I2C1, I2C2, I2C3, UART1,
UART2, McBSP1, McBSP5, GPTIMER10,
GPTIMER11, Mailbox, McSPI1,
McSPI2, McSPI3, McSPI4,
MMC/SD/SDIO1, MMC/SD/SDIO2,
HDQ/1-Wire,
ICR, camera ISP, MODEM,
INTC, SR1, SR2, MPU INTC
MMC/SD/SDIO3,
HS USB OTG
L4 interconnect
(emulation)
L4 interconnect (wake-up)
GPTIMER1, WDT2,
GPIO1, 32KTIMER
External peripherals ports
External peripherals ports
L3 interconnect
L4
USB
HS-OTG
L4
L4L4L4
OCM
RAM
Emulation, trace, and
debug modules
memmap-001
External and stacked memories
Stacked memories
TI Confidential — NDA Restrictions
www.ti.com Introduction
Figure 2-1. Interconnect Overview
SWPU176A– October 2009 Memory Mapping 203
3.12.2.2 Memory
Micro processor unit has a 32 bit address port , allowing it to handle a 4 GB space divided into several regions.
The Memory map is composed of a memory space and dedicated space Interconnect of the devices and the main
modules and subsystems in the platform.