3. TECHNICAL BRIEF
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Copyright © 2011 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
camisp-001
Device
L3
interconnect
Camera
ISP
L4
interconnect
CAM_IRQ0
MPU
subsystem
INTC
CAM_IRQ1
PRCM
CAM_MCLK
CAM_ICLK
CAM_FCLK
IVA2.2
subsystem
csi2_dx0 / ccpv2_dx0 / cam_d[6]
csi2_dy0 / ccpv2_dy0 / cam_d[7]
csi2_dx1 / ccpv2_dx1 / cam_d[8]
csi2_dy1 / ccpv2_dy1 / cam_d[9]
csi2_dx0 / ccpv2_dx0
csi2_dx1 / ccpv2_dx1
csi2_dy1 / ccpv2_dy1
csi2_dx2 / cam_d[1]
csi2_dy2 / cam_d[0]
CSIPHY1
CSIPHY2
STANDBY
hardware
handshake
INTC
cam_strobe
cam_global_reset
cam_shutter
cam_wen
cam_pclk
cam_xclka
CSI2A
CSI1 / CCP2B
CSI2C
cam_hs
cam_vs
cam_fld
cam_xclkb
CPI
Legend:
CPI input when PHY’s configured in GPI mode(cam_d signals)
Serial-to-Parallel converted data stream
(1)(2)
(1)(2)
(1)(2)
(1)(2)
(1)(2)
(1)(2)
(2)
(2)
(1)(2)
(1)(2)
(1)(2)
(1)(2)
csi2_dy0 / ccpv2_dy0
CSI2_96M__FCLK
cam_d[11:10]
cam_d[5:2]
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Camera ISP Overview
Figure 6-1. Camera ISP Overview Diagram
(1) The mode for each PHY can be selected from CSI2, CSI1/CCP2B, and GPI at
SCM.CONTROL_CAMERA_PHY_CTRL register. It can also control the connection between one of the
PHY's and CSI1/CCP2B receiver via multiplexing.
(2) There is no top-level muxmode (padconf SCM register) control bit for the different camera modes supported
by the interfaces. If one or another of the interfaces is enabled, then the camera input signals will be
automatically routed to the corresponding ISP receiver depending on the PHY operating mode settings
(SCM.CONTROL_CAMERA_PHY_CTRL register)
SWPU176A–October 2009 Camera Image Signal Processor 1155
3.12.2.4 Camera ISP
The camera ISP is a key component for imaging and video applications such as video preview, video record , and still
image capture with or without digital zooming.
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