LG LG-P970 - Page 76

3. TECHNICAL BRIEF
- 76 -
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ELIMINA
RY
17.4 HS I
2
C Functional Description
17.4.1 HS I
2
C Block Diagram
I2C _IRQi
I2C _FCLKi
I2C _ICLKi
I2C _RESETi
I2C-021
Device
MPU
INTC
L4-Core interconnect
PRCM
sDMA
controller
i2c _scli
i2c _sdai
i2c _sccbei
I2Ci
I
C and SCCB interface
2
FIFOs
Master/slave
control
Internal interface
Registers
Test
control
Clock/reset
control
I2C _DMA_TXi
I2C _DMA_RXi
I2C _SWAKEUPi
17.4.2 HS I
2
C Transmit Mode in I
2
C Mode
TI Confidential — NDA Restrictions
HS I
2
C Functional Description www.ti.com
Figure 17-21 is a functional block diagram of the HS I
2
C controllers.
Figure 17-21. HS I
2
C Controllers Functional Block Diagram
Note: The i2c1_sccbe and i2c4_sccbe signal is not available. The i2c4 does not have SWAKEUP
request. It also gets its RESET signal from the PRCM reset manager.
The three HS I
2
C controllers can be configured in F/S I
2
C mode, in HS I
2
C mode, or in SCCB mode. The
operation mode is selected by configuring the I2Ci.I2C_CON[13:12] OPMODE bit field. Table 17-10 lists
the available operation modes.
Table 17-10. HS I
2
C Operation Mode Selection
Operation Mode I2Ci.I2C_CON[13:12] OPMODE Bit Field Value
F/S I
2
C 0x0
HS I
2
C 0x1
SCCB 0x2
Reserved (not used) 0x3
This mode is available for master or slave. The master and slave modes are configurable with the
I2Ci.I2C_CON[10] MST bit (0: slave mode; 1: master mode).
In master mode, the transmit mode is configured by setting the I2Ci.I2C_CON[9] TRX bit to 1. The MPU
subsystem puts the data to transmit in the TX FIFO by writing to the I2Ci.I2C_DATA[7:0] DATA bit field.
2862 SWPU176A– October 2009
Multimaster High-Speed I
2
C Controller
3.12.2.6 I2C
The device contains four multimaster high speed inter integrated circuit controllers.