3. TECHNICAL BRIEF
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General-Purpose Interface Overview
Figure 25-1. General-Purpose Interface Overview
Each channel in GPIOs has the following features:
• The GPIOi.GPIO_OE register controls the output capability for each pin.
• The output line level reflects the value written in the GPIOi.GPIO_DATAOUT register through the level
4 (L4) interconnect.
• The input line can be fed to GPIO through an optional and configurable debounce cell. (The
debouncing time value is global for all ports of one GPIO module, so up to five different debouncing
time values are possible.)
• The input line value is sampled into the GPIOi.GPIO_DATAIN register and can be read through the L4
interconnect.
• In active mode, the input line can be used through level and edge detectors to trigger synchronous
interrupts. The edge (rising, falling, or both) or the level (logical 0, logical 1, or both) used can be
configured.
• In idle mode, the input line can be used to activate the asynchronous wake-up request (on edge
detection: Rising edge, falling edge, or both).
The module provides an alternative to the atomic test and set operations for the following registers:
• GPIOi.GPIO_DATAOUT
• GPIOi.GPIO_IRQENABLE1
• GPIOi.GPIO_IRQENABLE2
• GPIOi.GPIO_WAKEUPENABLE
For these registers, the modules implement the set-and-clear protocol register update (see
Section 25.5.2, Set and Clear Instructions).
SWPU176A– October 2009 General-Purpose Interface 3545
3.12.2.10 General Purpose IO
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