117
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Input/Output Function
11, 57 DGND G Digital Ground.
40 AGND G Analog Ground.
32 CLKIN_A I Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only
(27 MHz).
63 CLKIN_B I Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan
mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV mode. This
clock is only used in dual modes.
36, 45 COMP2, COMP1 O Compensation Pin for DACs. Connect 0.1 F capacitor from COMP pin
to V
AA
.
44 DAC A O CVBS/Green/Y/Y Analog Output.
43 DAC B O Chroma/Blue/U/Pb Analog Output.
42 DAC C O Luma/Red/V/Pr Analog Output.
39 DAC D O In SD Only Mode: CVBS/Green/Y Analog Output.
In HD Only mode and simultaneous HD/SD mode: Y/ Green [HD] Analog
Output.
38 DAC E O In SD Only Mode: Luma/ Blue/U Analog Output.
In HD Only mode and simultaneous HD/SD mode: Pr/ Red Analog Output.
37 DAC F O In SD Only Mode: Chroma/ Red/V Analog Output.
In HD Only mode and simultaneous HD/SD mode: Pb/ Blue [HD] Analog
Output.
23 P_HSYNC I Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode
and HD.
24 P_VSYNC I Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode
and HD.
25 P_BLANK I Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD.
48 S_BLANK I/O Video Blanking Control Signal for SD only.
50 S_HSYNC I/O Video Horizontal Sync Control Signal for SD Only.
49 S_VSYNC I/O Video Vertical Sync Control Signal for SD Only.
2–9, 12–13 Y9–Y0 I SD or Progressive Scan/HDTV Input Port for Y Data. Input port for inter-
leaved progressive scan data. The LSB is set up on Pin Y0. For 8-bit data
input, LSB is set up on Y2.
14–18, 26–30 C9–C0 I Progressive Scan/HDTV Input Port. In 4:4:4 Input mode, this port is used for
the Cb[Blue/U] data. The LSB is set up on Pin C0. For 8-bit data input, LSB
is set up on C2.
51–55, 58–62 S9–S0 I SD or Progressive Scan/HDTV Input Port for Cr [Red/V] Data in 4:4:4 Input
Mode. LSB is set up on Pin S0. For 8-bit data input, LSB is set up on S2.
33 RESET I T his input resets the on-chip timing generator and sets the ADV7314 into
default register setting. RESET is an active low signal.
35, 47 R
SET2
, R
SET1
I A 3040 resistor must be connected from this pin to AGND and is used
to control the amplitudes of the DAC outputs.
22 SCLK I I
2
C Port Serial Interface Clock Input.
21 SDA I/O I
2
C Port Serial Data Input/Output.
20 ALSB I TTL Address Input. This signal sets up the LSB of the I
2
C address. When
this pin is tied low, the I
2
C filter is activated, reducing noise on the I
2
C
interface.
1V
DD_IO
P Power Supply for Digital Inputs and Outputs.
10, 56 V
DD
P Digital Power Supply.
41 V
AA
P Analog Power Supply.
46 V
REF
I/O Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235 V).
34 EXT_LF I External Loop Filter for the Internal PLL.
31 RTC_SCR_TR I M ultifunctional Input. Real-time control (RTC) input, timing reset input,
subcarrier reset input.
19 I
2
C I This input pin must be tied high (V
DD_IO
) for the ADV7314 to interface
over the I
2
C port.
64 GND_IO Digital Input/Output Ground.
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