49
QX01:GL813
Pin Name Pin# Type
Pad Type
Description
CFPWR 1 B Tri-state Compact flash card power control
IODD0~15
37~40,
43~46,
2~5,
8~11
I Tri-state
IDE data bus 0~15
DVCC1~2 6,42 P Power
Digital VCC
DGND1~2 7,41 P Power
Digital ground
DO 12 I Tri-state
DO from EEPROM
CS1_ 13 O Tri-state
IDE chip select 1
DA2 / SK 14 O Tri-state IDE address 2 / SK to EEPROM
RESET# 15 I
Pull-high
HW reset
RPU 16 A U20mia 3.3v output
AVCC0~1 17,24 P Power Analog VCC
DPF 18 B U20mia Full speed DP
DPH 19 B U20mia High speed DP
DMF 20 B U20mia Full speed DM
DMH 21 B U20mia High speed DM
AGND0~1 22,27 P Power Analog ground
RREF 23 - U20mia Reference resister connect (*)
X2 25 B Clock Crystal output
X1 26 I Clock Crystal input, 12Mhz
CFDET 28 I Tri-state Compact flash card detect
TEST 29 I Pull-low TEST mode input
CS0_ 30 O Tri-state IDE Chip select 0
DA0 31 O Tri-state IDE address 0
DA1 / DI 32 O Tri-state IDE address 1 / DI to EEPROM
INTRQ 33 I Tri-state IDE Interrupt request
IORDY 34 I Tri-state IDE IO ready
DIOR_ 35 O Tri-state IDE read signal
DIOW_ 36 O Tri-state IDE write signal
CS 47 O Tri-state CS to EEPROM
CFRST 48 B Tri-state Compact Flash Card HW reset
Note: (*) RREF must be connected with a 510 ȍ resister to ground.
Pin Name Pin# Type
Pad Type
Description
NC
1~4,
13,14,
27~30,
51~54,
58,75,
77~80
- - No connection
GPIO7~8 100,5 B Tri-state GPIO7~8 (*)
GPIO5~6 6,7 B Tri-state GPIO5~6
IODD0~15
86~89,
92~95,
8~11,
16~19
B Tri-state IDE data bus 0 ~ 15
DVCC1~2 12,91 P Power Digital VCC
DGND1~2 15,90 P Power Digital ground
CBLID_ 20 I Tri-state Cable select input
NC/ECPURD/
EROMD0
21 I Pull-low
NC: Embedded CPU mode
ECPURD: Read signal when external CPU mode
EROMD0: Data0 when external ROM mode
NC/ECPUWR
/EROMD1
22 I Pull-low
NC: Embedded CPU mode
ECPUWR: Write signal when external CPU mode
EROMD1: Data1 when external ROM mode
NC/ECPUA5/
EROMD2
23 I Pull-low
NC: Embedded CPU mode
ECPUA5: Address5 when external CPU mode
EROMD2: Data2 when external ROM mode
NC/ECPUA4/
EROMD3
24 I Pull-low
NC: when embedded CPU mode
ECPUA4: Address4 when external CPU mode
EROMD3: Data3 when external ROM mode
NC/ECPUA3/
EROMD4
25 I Pull-low
NC: Embedded CPU mode
ECPUA3: Address3 when external CPU mode
EROMD4: Data4 when external ROM mode
NC/ECPUA2/
EROMD5
26 I Pull-low
NC: Embedded CPU mode
ECPUA2: Address2 when external CPU mode
EROMD5: Data5 when external ROM mode
NC/ECPUA1/
EROMD6
31 I Pull-low
NC: Embedded CPU mode
ECPUA1: Address1 when external CPU mode
EROMD6: Data6 when external ROM mode
NC/ECPUA0/
EROMD7
32 I Pull-low
NC: Embedded CPU mode
ECPUA0: Address0 when external CPU mode
EROMD7: Data7 when external ROM mode
NC/ECPUD7/
EROMD8
33 B Pull-low
NC: Embedded CPU mode
ECPUD7: Data7 when external CPU mode
EROMD8: Data8 when external ROM mode
NC/ECPUD6/
EROMD9
34 B Pull-low
NC: Embedded CPU mode
ECPUD6: Data6 when external CPU mode
EROMD9: Data9 when external ROM mode
NC/ECPUD5/
EROMD10
35 B Pull-low
NC: Embedded CPU mode
ECPUD5: Data5 when external CPU mode
EROMD10: Data10 when external ROM mode
NC/ECPUD4/
EROMD11
36 B Pull-low
NC: Embedded CPU mode
ECPUD4: Data4 when external CPU mode
EROMD11: Data11 when external ROM mode
NC/ECPUD3/
EROMD12
37 B Pull-low
NC: Embedded CPU mode
ECPUD3: Data3 when external CPU mode
EROMD12: Data12 when external ROM mode
NC/ECPUD2/
EROMD13
38 B Pull-low
NC: Embedded CPU mode
ECPUD2: Data2 when external CPU mode
EROMD13: Data13 when external ROM mode
CS1_ 39 O Tri-state Chip select 1
RESET# 41 I
Pull-hig
h
Reset pin
RPU 42 A U20mia 3.3v output
AVCC0~1 43,50 P Power Analog VCC
DPF 44 B U20mia Full speed DP
DPH 45 B U20mia High speed DP
DMF 46 B U20mia Full speed DM
DMH 47 B U20mia High speed DM
AGND0~1 48,57 P Power Analog ground
RREF 49 U20mia Reference resister connect (*)
X2 55 B Clock Crystal output
X1 56 I Clock Crystal input, 12Mhz
NC/ECPUD1/
EROMA0
59 B Pull-low
NC: Embedded CPU mode
ECPUD1: Data1 when external CPU mode
EROMA0: Address0 when external ROM mode
NC/ECPUD0/
EROMA1
60 B Pull-low
NC: Embedded CPU mode
ECPUD0: Data0 when external CPU mode
EROMA1: Address1 when external ROM mode
GPIO19 61 B Pull-low GPIO19
GPIO18/GPIO
18/EROMA11
62 B Pull-low
GPIO18: for embedded or external CPU mode
EROMA11: Address11 when external ROM mode
GPIO17/GPIO
17/EROMA10
63 B Pull-low
GPIO17: For embedded or external CPU mode
EROMA10: Address10 when external ROM mode
CS0_ 64 O Tri-state Chip select 0
DA0~2
65,66,
40
O Tri-state IDE address 0~2
GPIO16/GPIO
16/EROMA9
67 B Pull-low
GPIO16: For embedded or external CPU mode
EROMA9: Address9 when external ROM mode
GPIO15/GPIO
15/EROMA8
68 B Pull-low
GPIO15: For embedded or external CPU mode
EROMA8: Address8 when external ROM mode
GPIO14/GPIO
15/EROMA7
69 B Pull-low
GPIO14: For embedded or external CPU mode
EROMA7: Address7 when external ROM mode
GPIO13/GPIO
14/EROMA6
70 B Pull-low
GPIO13: For embedded or external CPU mode
EROMA6: Address6 when external ROM mode
INTRQ 71 I Tri-state IDE interrupt input
DMACK_ 72 O Tri-state IDE acknowledge
IORDY 73 I
Pull-high
IDE ready
DIOR_ 74 O Tri-state IDE read signal
DIOW_ 76 O Tri-state IDE write signal
GPIO12/GPIO
13/EROMA5
81 B Pull-low
GPIO12: For embedded or external CPU mode
EROMA5: Address5 when external ROM mode
GPIO11/GPIO
12/EROMA4
82 B Pull-low
GPIO11: For embedded or external CPU mode
EROMA4: Address4 when external ROM mode
GPIO10/GPIO
10/EROMA3
83 B Pull-low
GPIO10: For embedded or external CPU mode
EROMA3: Address3 when external ROM mode
GPIO9/GPIO9
/EROMA2
84 B Pull-low
GPIO9: For embedded or external CPU mode
EROMA2: Address2 when external ROM mode
DMARQ 85 I Pull-low IDE request
GPIO1~4 96~99 B
Pull-high
GPIO1~4
Note: (*) When operating in default mode: GPIO7 is the IDE reset input, GPIO8 is used to control the
power input of IDE device.
Notation:
Type O Output
I Input
B Bi-directional
B/I Bi-directional, default input
B/O Bi-directional, default output
P Power / Ground
A Analog
SO Automatic output low when suspend
pu Internal pull up
pd Internal pull down
odpu Open drain with internal pull up
Compact
Flash
Controller
Engine
CPU Control Register
CONTROL FIFO
RXFIFO 1
TXFIFO 1
TXFIFO 0
RXFIFO 0
SIE
UTMI
LOGIC
USB2.0
TXCVR
ClkgenX40
12HMz
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