dsPIC30F Quadrature Encoder Interface Module
© 2005 Microchip Technology Inc.
Page 7
© 2005 Microchip Technology Incorporated. All Rights Reserved. dsPIC30F Quadrature Encoder Interface Module 7
Digital Filters
O Multiple clock options to digital filter
O Tcy, 2Tcy, 4Tcy, 8Tcy, 16Tcy, …, 256Tcy
O Signal must be stable for 3 clock cycles
O Adjust clock divide bits to change noise
filtering characteristics
O Use of digital filter generates latency
The digital filters are responsible for rejecting noise from the three inputs. The
instruction cycle clock can be divided down by 2 , 4, 16, 32, 64, 128, 256 before
being used in the filter. The lower the clock frequency the lower frequencies are
rejected by the filter.
The prescaled clock is used to sample the input signal: if and only if three
consecutive samples have the same value the input is considered stable and
the value is output from the filter. One of the effects of this sampling is an
added latency, because there is a “propagation delay” of the input signal
through the filter.
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