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dsPIC30F
Microchip Technology dsPIC30F Family Reference Manual
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© 2004 Microchip Technology Inc.
DS70046C
dsPIC30F
Family Refer
ence Manual
High Performance
Digital Signal Controllers
2
Table of Contents
Table of Contents
3
Section 1. Introduction
11
Introduction
12
Manual Objective
12
Device Structure
13
Development Support
14
Style and Symbol Conventions
14
Related Documents
16
Revision History
17
Introduction
20
Section 2. Cpu
21
Programmer's Model
22
Software Stack Pointer
26
CPU Register Descriptions
29
Arithmetic Logic Unit (ALU)
35
DSP Engine
36
Divide Support
45
Instruction Flow Types
45
Loop Constructs
48
Address Register Dependencies
53
Related Application Notes
58
Revision History
59
Introduction
62
Section 3. Data Memory
63
Data Space Address Generator Units (Agus)
65
Modulo Addressing
67
Bit-Reversed Addressing
74
Control Register Descriptions
78
Related Application Notes
83
Revision History
84
Section 4. Program Memory
85
Program Memory Address Map
86
Program Counter
88
Data Access from Program Memory
88
Program Space Visibility from Data Space
92
Program Memory Writes
94
Related Application Notes
95
Revision History
96
Introduction
98
Run-Time Self-Programming (RTSP)
98
Section 5. Flash and Eeprom Programming
99
Control Registers
101
Run-Time Self-Programming (RTSP)
105
Data EEPROM Programming
110
Design Tips
116
Related Application Notes
117
Revision History
118
Section 6. Reset Interrupts
119
Introduction
120
Non-Maskable Traps
124
Interrupt Processing Timing
129
Interrupt Control and Status Registers
132
Interrupt Setup Procedures
160
Design Tips
162
Related Application Notes
163
Revision History
164
Introduction
166
Section 7. Oscillator
167
CPU Clocking Scheme
168
Oscillator Configuration
169
Oscillator Control Register (OSCCON)
170
11 = Primary Oscillator
171
Primary Oscillator
173
Crystal Oscillators/Ceramic Resonators
174
Determining Best Values for Crystals, Clock Mode, C1, C2 and Rs
176
External Clock Input
177
External RC Oscillator
178
Phase Locked Loop (PLL)
182
Low Power 32 Khz Crystal Oscillator
183
Oscillator Start-Up Timer (OST)
183
Internal Fast RC Oscillator (FRC)
183
Internal Low Power RC (LPRC) Oscillator
184
Fail-Safe Clock Monitor (FSCM)
184
Programmable Oscillator Postscaler
185
Clock Switching Operation
186
Design Tips
190
Related Application Notes
191
Revision History
192
Section 8. Reset
193
Introduction
194
POR: Power-On Reset
194
External Reset (EXTR)
199
Software RESET Instruction (SWR)
199
Watchdog Time-Out Reset (WDTR)
199
Brown-Out Reset (BOR)
200
Using the RCON Status Bits
202
Device Reset Times
203
Device Start-Up Time Lines
205
Special Function Register Reset States
208
Design Tips
209
Related Application Notes
210
Revision History
211
Introduction
214
Section 9. Low Voltage Detect (Lvd)
215
LVD Operation
217
Design Tips
218
Related Application Notes
219
Revision History
220
Section 10. Watchdog Timer and Power Saving Modes
221
Introduction
222
Power Saving Modes
222
Sleep Mode
222
Idle Mode
224
Interrupts Coincident with Power Save Instructions
225
Watchdog Timer
226
Design Tips
229
Related Application Notes
230
Revision History
231
Section 11. I/O Ports
233
Introduction
234
I/O Port Control Registers
235
Peripheral Multiplexing
236
Port Descriptions
237
Change Notification (CN) Pins
237
CN Operation in Sleep and Idle Modes
238
Related Application Notes
241
Revision History
242
Section 12. Timers
243
Introduction
244
Timer Variants
245
Control Registers
248
Modes of Operation
251
Timer Prescalers
256
Timer Interrupts
256
Reading and Writing 16-Bit Timer Module Registers
257
Low Power 32 Khz Crystal Oscillator Input
257
32-Bit Timer Configuration
258
32-Bit Timer Modes of Operation
260
Reading and Writing into 32-Bit Timers
263
Timer Operation in Power Saving States
263
Peripherals Using Timer Modules
264
Design Tips
266
Related Application Notes
267
Revision History
268
Section 13. Input Capture
269
Introduction
270
Input Capture Registers
271
Timer Selection
272
Input Capture Event Modes
272
Capture Buffer Operation
276
Input Capture Interrupts
277
UART Autobaud Support
277
Input Capture Operation in Power Saving States
278
I/O Pin Control
278
Design Tips
280
Related Application Notes
281
Revision History
282
Section 14. Output Compare
283
Introduction
284
Output Compare Registers
285
Modes of Operation
286
Output Compare Operation in Power Saving States
305
I/O Pin Control
305
Design Tips
308
Related Application Notes
309
Revision History
310
Introduction
312
Section 15. Motor Control Pwm
313
Control Registers
314
PWM Time Base
326
PWM Duty Cycle Comparison Units
330
Complementary PWM Output Mode
334
Dead Time Control
335
Independent PWM Output Mode
338
PWM Output Override
339
PWM Output and Polarity Control
342
PWM Fault Pins
342
PWM Update Lockout
345
PWM Special Event Trigger
345
Operation in Device Power Saving Modes
346
Special Features for Device Emulation
347
Related Application Notes
350
Revision History
351
Section 16. Quadrature Encoder Interface (Qei)
353
Module Introduction
354
Control and Status Registers
356
Programmable Digital Noise Filters
361
Quadrature Decoder
362
16-Bit Up/Down Position Counter
364
Using QEI as an Alternate 16-Bit Timer/Counter
368
Quadrature Encoder Interface Interrupts
369
I/O Pin Control
370
QEI Operation During Power Saving Modes
371
Effects of a Reset
371
Design Tips
373
Related Application Notes
374
Revision History
375
Section 17. 10-Bit A/D Converter
377
Introduction
378
Control Registers
380
A/D Result Buffer
380
A/D Terminology and Conversion Sequence
387
A/D Module Configuration
389
Selecting the Voltage Reference Source
389
Selecting the A/D Conversion Clock
389
Selecting Analog Inputs for Sampling
390
Enabling the Module
392
Specifying the Sample/Conversion Sequence
392
How to Start Sampling
393
How to Stop Sampling and Start Conversions
394
Controlling Sample/Conversion Operation
405
Specifying How Conversion Results Are Written into the Buffer
406
Conversion Sequence Examples
407
A/D Sampling Requirements
421
Reading the A/D Result Buffer
422
Transfer Function
423
A/D Accuracy/Error
423
Connection Considerations
423
Initialization
424
Operation During Sleep and Idle Modes
425
Effects of a Reset
425
Design Tips
427
Related Application Notes
428
Revision History
429
Section 18. 12-Bit A/D Converter
431
Revision History
431
Introduction
432
Control Registers
434
A/D Result Buffer
434
A/D Terminology and Conversion Sequence
440
A/D Module Configuration
441
Selecting the Voltage Reference Source
441
Selecting the A/D Conversion Clock
442
Selecting Analog Inputs for Sampling
442
Enabling the Module
444
How to Start Sampling
444
How to Stop Sampling and Start Conversions
444
Controlling Sample/Conversion Operation
449
Specifying How Conversion Results Are Written into the Buffer
449
Conversion Sequence Examples
451
A/D Sampling Requirements
456
Reading the A/D Result Buffer
457
Transfer Function
458
A/D Accuracy/Error
458
Connection Considerations
458
Initialization
459
Operation During Sleep and Idle Modes
460
Effects of a Reset
460
Design Tips
462
Related Application Notes
463
Revision History
464
Section 19. Uart
465
Introduction
466
Control Registers
467
UART Baud Rate Generator (BRG)
472
UART Configuration
474
UART Transmitter
475
UART Receiver
478
Using the UART for 9-Bit Communication
482
Receiving Break Characters
483
Initialization
484
Other Features of the UART
485
UART Operation During CPU Sleep and Idle Modes
485
Design Tips
487
Related Application Notes
488
Revision History
489
Section 20. Serial Peripheral Interface (Spi™)
491
Introduction
492
Status and Control Registers
494
Modes of Operation
497
SPI Master Mode Clock Frequency
509
Operation in Power Save Modes
510
Related Application Notes
513
Revision History
514
Section 21. Inter-Integrated Circuit™ (I2C™)
515
Overview
516
I 2 C Bus Characteristics
518
Control and Status Registers
521
Enabling I 2 C Operation
527
Communicating as a Master in a Single Master Environment
529
Communicating as a Master in a Multi-Master Environment
543
Communicating as a Slave
546
Connection Considerations for I
561
Module Operation During PWRSAV Instruction
563
Effects of a Reset
563
Design Tips
564
Related Application Notes
565
Revision History
566
Section 22. Data Converter Interface (DCI)
567
Introduction
568
Control Register Descriptions
568
Codec Interface Basics and Terminology
574
DCI Operation
576
Using the DCI Module
583
Operation in Power Saving Modes
594
Registers Associated with DCI
594
Design Tips
596
Related Application Notes
597
Revision History
598
Section 23. Can Module
599
Introduction
600
Control Registers for the CAN Module
600
CAN Module Features
626
CAN Module Implementation
627
CAN Module Operation Modes
634
Message Reception
637
Transmission
647
Error Detection
656
CAN Baud Rate
658
Interrupts
662
Time-Stamping
663
CAN Module I/O
663
Operation in CPU Power Saving Modes
664
CAN Protocol Overview
666
Related Application Notes
670
Revision History
671
Section 24. Device Configuration
673
Introduction
674
Device Configuration Registers
674
Configuration Bit Descriptions
679
Device Identification Registers
680
Related Application Notes
681
Revision History
682
Section 25. Development Tool Support
683
Introduction
684
Microchip Hardware and Language Tools
684
Third Party Hardware/Software Tools and Application Libraries
688
Dspic30F Hardware Development Boards
693
Related Application Notes
697
Revision History
698
Section 26. Appendix
699
Appendix A: I2C™ Overview
700
Appendix B: CAN Overview
710
Appendix C: Codec Protocol Overview
723
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Microchip Technology dsPIC30F Specifications
General
Brand
Microchip Technology
Model
dsPIC30F
Category
Controller
Language
English
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