© 2004 Microchip Technology Inc. DS70068C-page 21-7
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.2.2.6 Slave Reply
Now the slave transmits the data byte driving the SDA line, while the master continues to
originate clocks but releases its SDA drive.
21.2.2.7 Master Acknowledge
During reads, a master must terminate data requests to the slave by NOT Acknowledging
(generate a “NACK”) on the last byte of the message.
21.2.2.8 Stop Message
The master sends Stop to terminate the message and return the bus to an Idle state.
21.3 Control and Status Registers
The I
2
C module has six user-accessible registers for I
2
C operation. The registers are accessible
in either Byte or Word mode. The registers are shown in Figure 21-5 and listed below:
• Control Register (I2CCON): This register allows control of the I
2
C operation.
• Status Register (I2CSTAT): This register contains status flags indicating the module state
during I
2
C operation.
• Receive Buffer Register (I2CRCV): This is the buffer register from which data bytes can be
read. The I2CRCV register is a read only register.
• Transmit Register (I2CTRN): This is the transmit register; bytes are written to this register
during a transmit operation. The I2CTRN register is a read/write register.
• Address Register (I2CADD): The I2CADD register holds the slave device address.
• Baud Rate Generator Reload Register (I2CBRG): Holds the baud rate generator reload
value for the I
2
C module baud rate generator.
Figure 21-5: I
2
C Programmer’s Model
Bit 7
Bit 0
I2CRCV (8 bits)
Bit 7
Bit 0
I2CTRN (8 bits)
Bit 8
Bit 0
I2CBRG (9 bits)
Bit 15
Bit 0
I2CCON (16 bits)
Bit 15
Bit 0
I2CSTAT (16 bits)
Bit 9
Bit 0
I2CADD (10 bits)
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