Microchip Technology dsPIC30F - I 2 C Bus Characteristics

dsPIC30F Family Reference Manual
DS70068C-page 21-4 © 2004 Microchip Technology Inc.
21.2 I
2
C Bus Characteristics
The I
2
C bus is a two-wire serial interface. Figure 21-2 is a schematic of a typical I
2
C connection
between the dsPIC30F device and a 24LC256 I
2
C serial EEPROM.
The I
2
C interface employs a comprehensive protocol to ensure reliable transmission and
reception of data. When communicating, one device is the “master” which initiates transfer on
the bus and generates the clock signals to permit that transfer, while the other device(s) acts as
the “slave” responding to the transfer. The clock line, “SCL”, is output from the master and input
to the slave, although occasionally the slave drives the SCL line. The data line, “SDA”, may be
output and input from both the master and slave.
Because the SDA and SCL lines are bidirectional, the output stages of the devices driving the
SDA and SCL lines must have an open drain in order to perform the wired-AND function of the
bus. External pull-up resistors are used to ensure a high level when no device is pulling the line
down.
In the I
2
C interface protocol, each device has an address. When a master wishes to initiate a
data transfer, it first transmits the address of the device that it wishes to “talk” to. All devices
“listen” to see if this is their address. Within this address, bit ‘0’ specifies if the master wishes to
read from or write to the slave device. The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data transfer. That is, they can be thought of as
operating in either of these two relations:
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
In both cases, the master originates the SCL clock signal.
Figure 21-2: Typical I
2
C Interconnection Block Diagram
MCLR
VDD
VSS
OSC1
OSC2
SCL
SDA
dsPIC30F
4.7 µF
XTAL
0.1 µF
VDD
VSS
SDA
SCL
V
DD
A0
A1
A2
WP
VDD VDD
VDD
5 kΩ
24LC256