Microchip Technology dsPIC30F - Communicating as a Master in a Single Master Environment

© 2004 Microchip Technology Inc. DS70068C-page 21-15
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.5 Communicating as a Master in a Single Master Environment
Typical operation of the I
2
C module in a system is using the I
2
C to communicate with an I
2
C
peripheral, such as an I
2
C serial memory. In an I
2
C system, the master controls the sequence
of all data communication on the bus. In this example, the dsPIC30F and its I
2
C module have
the role of the single master in the system. As the single master, it is responsible for generating
the SCL clock and controlling the message protocol.
In the I
2
C module, the module controls individual portions of the I
2
C message protocol,
however, sequencing of the components of the protocol to construct a complete message is a
software task.
For example, a typical operation in a single master environment may be to read a byte from an
I
2
C serial EEPROM. This example message is depicted in Figure 21-7.
To accomplish this message, the software will sequence through the following steps.
1. Assert a Start condition on SDA and SCL.
2. Send the I
2
C device address byte to the slave with a write indication.
3. Wait for and verify an Acknowledge from the slave.
4. Send the serial memory address high byte to the slave.
5. Wait for and verify an Acknowledge from the slave.
6. Send the serial memory address low byte to the slave.
7. Wait for and verify an Acknowledge from the slave.
8. Assert a Repeated Start condition on SDA and SCL.
9. Send the device address byte to the slave with a read indication.
10. Wait for and verify an Acknowledge from the slave.
11. Enable master reception to receive serial memory data.
12. Generate an ACK or NACK condition at the end of a received byte of data.
13. Generate a Stop condition on SDA and SCL.
Figure 21-7: A Typical I
2
C Message: Read Of Serial EEPROM (Random Address Mode)
The I
2
C module supports Master mode communication with the inclusion of Start and Stop
generators, data byte transmission, data byte reception, Acknowledge generator and a baud
rate generator.
Generally, the software will write to a control register to start a particular step, then wait for an
interrupt or poll status to wait for completion.
Subsequent sub-sections detail each of these operations.
Bus
Master
SDA
A
C
K
N
A
C
A
C
K
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T
Address
Byte
EE ADDR
High Byte
EE ADDR
Low Byte
Address
Byte
Data
Byte
S
T
A
R
T
S 1010
AAA
0
210
R 1010
AAA
1
210
P
K
Slave
SDA
Activity
N
AAAA
E
R
R
/
W
R
/
W
Output
Output
I
D
L
E
I
D
L
E
Note: The I
2
C module does not allow queueing of events. For instance, the software is not
allowed to initiate a Start condition and immediately write the I2CTRN register to ini-
tiate transmission before the Start condition is complete. In this case, the I2CTRN
will not be written to and the IWCOL bit will be set, indicating that this write to the
I2CTRN did not occur.