dsPIC30F Family Reference Manual
DS70062C-page 15-32 © 2004 Microchip Technology Inc.
15.9 PWM Output and Polarity Control
The PENxx control bits in PWMCON1 enable each PWM output pin for use by the module.
When a pin is enabled for PWM output, the PORT and TRIS registers controlling the pin are
disabled.
In addition to the PENxx control bits, there are three device configuration bits in the FBORPOR
device configuration register that provide PWM output pin control.
• HPOL configuration bit
• LPOL configuration bit
• PWMPIN configuration bit
These three configuration bits work in conjunction with the PWM enable bits (PENxx) located in
PWMCON1. The configuration bits ensure that the PWM pins are in the correct states after a
device reset occurs.
15.9.1 Output Polarity Control
The polarity of the PWM I/O pins is set during device programming via the HPOL and LPOL
configuration bits in the FBORPOR Device Configuration register. The HPOL configuration
bit sets the output polarity for the high-side PWM outputs PWM1H-PWM4H. The LPOL
configuration bit sets the output polarity for the low-side PWM outputs PWM1L-PWM 4L.
If the polarity configuration bit is programmed to a ‘1’, the corresponding PWM I/O pins will have
active-high output polarity. If the polarity configuration bit is programmed to a ‘0’, then the
corresponding PWM pins will have active-low polarity.
15.9.2 PWM Output Pin Reset States
The PWMPIN configuration bit determines the behavior of the PWM output pins on a device
reset and can be used to eliminate external pull-up/pull-down resistors connected to the devices
controlled by the PWM module.
If the PWMPIN configuration bit is programmed to a ‘1’, the PENxx control bits will be cleared
on a device reset. Consequently, all PWM outputs will be tri-stated and controlled by the
corresponding PORT and TRIS registers.
If the PWMPIN configuration bit is programmed to a ‘0’, the PENxx control bits will be set on a
device reset. All PWM pins will be enabled for PWM output at the device reset and will be at
their inactive states as defined by the HPOL and LPOL configuration bits.
15.10 PWM Fault Pins
There are two Fault pins, FLTA and FLTB, associated with the PWM module. When asserted,
these pins can optionally drive each of the PWM I/O pins to a defined state. This action takes
place without software intervention so fault events can be managed quickly.
The Fault pins may have other multiplexed functions depending on the dsPIC device variant.
When used as a fault input, each Fault pin is readable via its corresponding PORT register. The
FLTA and FLTB pins function as active low inputs so that it is easy to wire-OR many sources to
the same input through an external pull-up resistor. When not used with the PWM module, these
pins may be used as general purpose I/O or another multiplexed function. Each Fault pin has its
own interrupt vector, Interrupt Flag bit, Interrupt Enable bit and Interrupt Priority bits associated
with it.
The function of the FLTA
pin is controlled by the FLTACON register and the function of the FLTB
pin is controlled by the FLTBCON register.
15.10.1 Fault Pin Enable Bits
The FLTACON and FLTBCON registers each have 4 control bits, FxEN1-FxEN4, that determine
whether a particular pair of PWM I/O pins is to be controlled by the fault input pin. To enable a
specific PWM I/O pin pair for fault overrides, the corresponding bit should be set in the
FLTACON or FLTBCON register.
If all enable bits are cleared in the FLTACON or FLTBCON registers, then that fault input pin has
no effect on the PWM module and no fault interrupts will be produced.
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