© 2004 Microchip Technology Inc. DS70056C-page 9-5
Section 9. Low Voltage Detect
Low Voltage
Detect (LVD)
9
9.2 LVD Operation
The LVD module adds robustness to the application because the device can monitor the state of
the device voltage. When the device voltage enters a voltage window near the lower limit of the
valid operating voltage range, the device can save values to ensure a “clean” shutdown.
Depending on the power source for the device, the supply voltage may decrease relatively
slowly. This means that the LVD module does not need to be constantly operating. To decrease
the current requirements, the LVD circuitry only needs to be enabled for short periods where the
voltage is checked. After doing the check, the LVD module may be disabled.
9.2.1 LVD Initialization Steps
The following steps are required to setup the LVD module:
1. If the external LVD input pin is used (LVDIN), ensure that all other peripherals multiplexed
on the pin are disabled and the pin is configured as an input by setting the appropriate bit
in the TRISx registers.
2. Write the desired value to the LVDL control bits (RCON<11:8>), which selects the desired
LVD threshold voltage.
3. Ensure that LVD interrupts are disabled by clearing the LVDIE bit (IEC2<10>).
4. Enable the LVD module by setting the LVDEN bit (RCON<12>).
5. Wait for the internal voltage reference to become stable by polling the BGST status bit
(RCON<13>), if required (see Section 9.1.2 “Internal Voltage Reference”).
6. Ensure that the LVDIF bit (IFS2<10>) is cleared before interrupts are enabled. If LVDIF is
set, the device V
DD may be below the chosen LVD threshold voltage.
7. Set LVD interrupts to the desired CPU priority level by writing the LVDIP<2:0> control bits
(IPC10<10:8>).
8. Enable LVD interrupts by setting the LVDIE control bit.
Once the V
DD has fallen below the programmed LVD threshold, the LVDIF bit will remain set.
When the LVD module has interrupted the CPU, one of two actions may be taken in the ISR:
1. Clear the LVDIE control bit to disable further LVD module interrupts and take the
appropriate shutdown procedures.
or
2. Decrease the LVD voltage threshold using the LVDL control bits and clear the LDVIF
status bit. This technique can be used to track a gradually decreasing battery voltage.
9.2.2 Current Consumption for LVD Operation
The LVD circuit relies on an internal voltage reference circuit that is shared with other peripheral
devices, such as the Brown-out Reset (BOR) module. The internal voltage reference will be
active whenever one of its associated peripherals is enabled. For this reason, the user may not
observe the expected change in current consumption when the LVD module is disabled.
9.2.3 Operation in Sleep and Idle Mode
When enabled, the LVD circuitry continues to operate during Sleep or Idle modes. If the device
voltage crosses the trip point, the LVDIF bit will be set.
The criteria for exiting from Sleep or Idle modes are as follows:
• If the LVDIE bit (IEC2<10>) is set, the device will wake from Sleep or Idle mode.
• If the assigned priority for the LVD interrupt is less than or equal to the current CPU priority,
the device will wake-up and continue code execution from the instruction following the
PWRSAV instruction that initiated the Sleep or Idle mode.
• If the assigned priority level for the LVD interrupt is greater than the current CPU priority,
the device will wake-up and the CPU exception process will begin. Code execution will
continue from the first instruction of the LVD ISR.
Note: The system design should ensure that the application software is given adequate
time to save values before the device exits the valid operating range, or is forced
into a Brown-out Reset.
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