Microchip Technology dsPIC30F - Peripheral Multiplexing

dsPIC30F Family Reference Manual
DS70058C-page 11-4 © 2004 Microchip Technology Inc.
11.3 Peripheral Multiplexing
When a peripheral is enabled, the use of any associated pin as a general purpose I/O pin is
disabled. The I/O pin may be read through the input data path, but the output driver for the I/O
port bit will be disabled.
An I/O port that shares a pin with another peripheral is always subservient to the peripheral. The
peripheral’s output buffer data and control signals are provided to a pair of multiplexers. The
multiplexers select whether the peripheral, or the associated port, has ownership of the output
data and control signals of the I/O pin. Figure 11-2 shows how ports are shared with other
peripherals, and the associated I/O pin to which they are connected.
Figure 11-2: Shared Port Structure Block Diagram
11.3.1 I/O Multiplexing with Multiple Peripherals
For some dsPIC30F devices, especially those with a small number of I/O pins, multiple peripheral
functions may be multiplexed on each I/O pin. Figure 11-2 shows an example of two peripherals
multiplexed to the same I/O pin.
The name of the I/O pin defines the priority of each function associated with the pin. The concep-
tual I/O pin, shown in Figure 11-2, has two multiplexed peripherals, ‘Peripheral A’ and
‘Peripheral B’ and is named “PERA/PERB/PIO”.
The I/O pin name is chosen so that the user can easily tell the priority of the functions assigned
to the pin. For the example shown in Figure 11-2, Peripheral A has the highest priority for control
of the pin. If Peripheral A and Peripheral B are enabled at the same time, Peripheral A will take
control of the I/O pins.
Note: In order to use PORTB pins for digital I/O, the corresponding bits in the ADPCFG
register must be set to ‘1’, even if the A/D module is turned off.
QD
CK
TRIS Latch
Data Bus
QD
CK
Data Latch
Read LAT
Read Port
Read TRIS
WR TRIS
PIO Module
WR LAT
WR Port
0
1
Peripheral A o.e.
0
1
Peripheral A Enable
Peripheral B Enable
Peripheral B o.e.
0
1
Peripheral A Data
0
1
Peripheral B Data
R
Peripheral A Input
R
Peripheral B Input
PERA/PERB/PIO
Peripheral Multiplexers
I/O pin