dsPIC30F Family Reference Manual
DS70054C-page 7-20 © 2004 Microchip Technology Inc.
7.14 Internal Low Power RC (LPRC) Oscillator
The LPRC oscillator is a component of the Watchdog Timer (WDT) and oscillates at a nominal
frequency of 512 kHz. The LPRC oscillator is the clock source for the Power-up Timer (PWRT)
circuit, WDT and clock monitor circuits. It may also be used to provide a low frequency clock
source option for applications where power consumption is critical, and timing accuracy is not
required.
7.14.1 Enabling the LPRC Oscillator
The LPRC oscillator is always enabled at a Power-on Reset because it is the clock source for
the PWRT. After the PWRT expires, the LPRC oscillator will remain ON if one of the following is
TRUE:
• The Fail-Safe Clock Monitor is enabled.
• The WDT is enabled.
• The LPRC oscillator is selected as the system clock (COSC<1:0> = 10).
If none of the above conditions is true, the LPRC will shut-off after the PWRT expires.
7.15 Fail-Safe Clock Monitor (FSCM)
The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event
of an oscillator failure. The FSCM function is enabled by programming the FCKSM bits
(Clock Switch and Monitor bits) in the FOSC Device Configuration register. Refer to Section
24. “Device Configuration” for further details. If the FSCM function is enabled, the LPRC
internal oscillator will run at all times (except during Sleep mode).
In the event of an oscillator failure, the FSCM will generate a clock failure trap and will switch the
system clock to the FRC oscillator. The user will then have the option to either attempt to restart
the oscillator or execute a controlled shutdown.
The FSCM module will take the following actions when switching to the FRC oscillator:
1. The COSC<1:0> bits are loaded with ‘01’.
2. The CF bit is set to indicate the clock failure.
3. The OSWEN control bit is cleared to cancel any pending clock switches.
7.15.1 FSCM Delay
On a POR, BOR or wake-up event from Sleep mode, a nominal 100 µs delay (TFSCM) may be
inserted before the FSCM begins to monitor the system clock source. The purpose of the FSCM
delay is to provide time for the oscillator and/or PLL to stabilize when the Power-up Timer
(PWRT) is not utilized. The FSCM delay will be generated after the internal System Reset signal,
SYSRST, has been released. Refer to Section 8. “Reset” for FSCM delay timing information.
The FSCM delay, T
FSCM, is applied when the FSCM is enabled and any of the following device
clock sources is selected as the system clock:
• EC+PLL
•XT+PLL
•XT
•HS
•XTL
•LP
Note: The oscillation frequency of the LPRC oscillator will vary depending on the device
voltage and operating temperature. Refer to the “Electrical Specifications” in the
specific device data sheet for further details.
Note: For more information about the oscillator failure trap, please refer to
Section 6. “Reset Interrupts”.
Note: Please refer to the “Electrical Specifications” section of the device data sheet for
T
FSCM specification values.
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