dsPIC30F Family Reference Manual
DS70066C-page 19-14 © 2004 Microchip Technology Inc.
19.5.4 Transmission of Break Characters
Setting the UTXBRK bit (UxSTA<11>) will force the UxTX line to ‘0’. UTXBRK overrides any other
transmitter activity. The user should wait for the transmitter to be Idle (TRMT = 1) before setting
UTXBRK.
To send a break character, the UTXBRK bit must be set by software and remain set for a mini-
mum of 13 baud clocks. The baud clock periods are timed in software. The UTXBRK bit is then
cleared by software to generate the Stop bit. The user must wait at least one or two baud clocks
to ensure a valid Stop bit(s) before loading the UTXBUF again or renewing transmitter activity.
19.6 UART Receiver
The receiver block diagram is shown in Figure 19-5. The heart of the receiver is the Receive
(Serial) Shift register (UxRSR). The data is received on the UxRX pin and is sent to the data
recovery block. The data recovery block operates at 16 times the baud rate, whereas the main
receive serial shifter operates at the baud rate. After sampling the UxRX pin for the Stop bit, the
received data in UxRSR is transferred to the receive FIFO (if it is empty).
The data on the UxRX pin is sampled three times by a majority detect circuit to determine if a
high or a low level is present at the UxRX pin. Figure 19-5 shows the sampling scheme.
19.6.1 Receive Buffer (UxRXB)
The UART receiver has a 4-deep, 9-bit wide FIFO receive data buffer. UxRXREG is a memory
mapped register that provides access to the output of the FIFO. It is possible for 4 words of data
to be received and transferred to the FIFO and a fifth word to begin shifting to the UxRSR register
before a buffer overrun occurs.
19.6.2 Receiver Error Handling
If the FIFO is full (four characters) and a fifth character is fully received into the UxRSR register,
the overrun error bit, OERR (UxSTA<1>), will be set. The word in UxRSR will be kept, but further
transfers to the receive FIFO are inhibited as long as the OERR bit is set. The user must clear
the OERR bit in software to allow further data to be received.
If it is desired to keep the data received prior to the overrun, the user should first read all five
characters, then clear the OERR bit. If the five characters can be discarded, the user can simply
clear the OERR bit. This effectively resets the receive FIFO and all prior received data is lost.
The framing error bit, FERR (UxSTA<2>), is set if a Stop bit is detected as a logic low level.
The parity error bit, PERR (UxSTA<3>), is set if a parity error has been detected in the data word
at the top of the buffer (i.e., the current word). For example, a parity error would occur if the parity
is set to be even, but the total number of ones in the data has been detected to be odd. The PERR
bit is irrelevant in the 9-bit mode. The FERR and PERR bits are buffered along with the
corresponding word and should be read before reading the data word.
Note: Sending a break character does not generate a transmitter interrupt.
Note: The UxRSR register is not mapped in data memory, so it is not available to the user.
Note: The data in the receive FIFO should be read prior to clearing the OERR bit. The
FIFO is reset when OERR is cleared, which causes all data in the buffer to be lost.
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