© 2004 Microchip Technology Inc. DS70066C-page 19-15
Section 19. UART
UART
19
19.6.3 Receive Interrupt
The UART receive interrupt flag (UxRXIF) is located in the corresponding Interrupt Flag Status
(IFS) register. The URXISEL<1:0> (UxSTA<7:6>) control bits determine when the UART receiver
generates an interrupt.
a) If URXISEL<1:0> = 00 or 01, an interrupt is generated each time a data word is
transferred from the Receive Shift register (UxRSR) to the receive buffer. There may be
one or more characters in the receive buffer.
b) If URXISEL<1:0> = 10, an interrupt is generated when a word is transferred from the
Receive Shift register (UxRSR) to the receive buffer and as a result, the receive buffer
contains 3 or 4 characters.
c) If URXISEL<1:0> = 11, an interrupt is generated when a word is transferred from the
Receive Shift register (UxRSR) to the receive buffer and as a result, the receive buffer
contains 4 characters (i.e., becomes full).
Switching between the three Interrupt modes during operation is possible.
While the URXDA and UxRXIF flag bits indicate the status of the UxRXREG register, the RIDLE
bit (UxSTA<4>) shows the status of the UxRSR register. The RIDLE status bit is a read only bit,
which is set when the receiver is Idle (i.e., the UxRSR register is empty). No interrupt logic is tied
to this bit, so the user has to poll this bit in order to determine if the UxRSR is Idle.
The URXDA bit (UxSTA<0>) indicates whether the receive buffer has data or whether the buffer
is empty. This bit is set as long as there is at least one character to be read from the receive
buffer. URXDA is a read only bit.
Figure 19-5 shows a block diagram of the UART receiver.
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