Microchip Technology dsPIC30F - Section 2. Cpu

© 2004 Microchip Technology Inc. DS70049C-page 2-3
Section 2. CPU
CPU
2
Figure 2-1: dsPIC30F CPU Core Block Diagram
Power-up
Timer
Oscillator
Start-up Timer
POR/BOR
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
MCLR
VDD, VSS
Low Voltage
Detect
UART1,
CAN2
Timing
Generation
CAN1,
16
PCH PCL
16
Program Counter
16-bit ALU
24
24
24
24
X Data Bus
IR
I
2
C™
DCI
PCU
10-bit or
Timers
Input
Capture
Module
Output
Compare
Module
16
16
16
16 x 16
W Reg Array
Divide
Support
Engine
DSP
ROM Latch
16
Y Data Bus
EA MUX
X RAGU
X WAGU
Y AGU
AVDD, AVSS
UART2
SPI2
16
16
16
16
16
16
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
(4 Kbytes)
RAM
X Data
(4 Kbytes)
RAM
Address
Latch
Address
Latch
Control Signals
to Various Blocks
16
SPI1,
Address Latch
Program Memory
(144 Kbytes)
Data Latch
Data EEPROM
(4 Kbytes)
I/O Ports
16
16
16
X Address Bus
Y Address Bus
16
Literal Data
12-bit ADC