Microchip Technology dsPIC30F - Message Reception

© 2004 Microchip Technology Inc. DS70070B-page 23-39
Section 23. CAN
CAN Module
23
23.6 Message Reception
This subsection describes CAN module message reception.
23.6.1 Receive Buffers
The CAN bus module has 3 receive buffers. However, one of the receive buffers is always
committed to monitoring the bus for incoming messages. This buffer is called the message
assembly buffer, MAB. So there are 2 receive buffers visible, RXB0 and RXB1, that can
essentially instantaneously receive a complete message from the protocol engine. The CPU can
be operating on one while the other is available for reception or holding a previously received
message.
The MAB holds the destuffed bit stream from the bus line to allow parallel access to the whole
data or remote frame for the acceptance match test and the parallel transfer of the frame to the
receive buffers. The MAB will assemble all messages received. These messages will be
transferred to the RXBn buffers only if the acceptance filter criterion are met. When a message
is received, the RXnIF flag (CiINTF<0> or CiINRF<1>) will be set. This bit can only be set by the
module when a message is received. The bit is cleared by the CPU when it has completed
processing the message in the buffer. This bit provides a positive lockout to ensure that the CPU
has finished with the message buffer. If the RXnIE bit (CiINTE<0> or CiINTE<1>) is set , an
interrupt will be generated when a message is received.
There are 2 programmable acceptance filter masks associated with the receive buffers, one for
each buffer.
When the message is received, the FILHIT bits (CiRX0CON<0> for Receive Buffer 0 and
CiRX1CON<2:0> for Receive Buffer 1) indicate the acceptance criterion for the message. The
number of the acceptance filter that enabled the reception will be indicated as well as a Status
bit that indicates that the received message is a remote transfer request.
Note: In the case of Receive Buffer 0, a limited number of Acceptance Filters can be used
to enable a reception. A single bit, FILHIT0 (CiRX0CON<0>) determines which of
the 2 filters, RXF0 or RXF1, enabled the message reception.