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Microchip Technology dsPIC30F - Connection Considerations for I

Microchip Technology dsPIC30F
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© 2004 Microchip Technology Inc. DS70068C-page 21-47
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.8 Connection Considerations for I
2
C Bus
By definition of the I
2
C bus being a wired AND bus connection, pull-up resistors on the bus are
required, shown as R
P in Figure 21-33. Series resistors, shown as RS are optional and used to
improve ESD susceptibility. The values of resistors R
P and RS depend on the following
parameters:
Supply voltage
Bus capacitance
Number of connected devices (input current + leakage current)
Because the device must be able to pull the bus low against R
P, current drawn by RP must be
greater than the I/O pin minimum sink current I
OL of 3 mA at VOL(MAX) = 0.4V for the device
output stage. For example, with a supply voltage of V
DD = 5V +10%:
R
P(MIN) = (VDD(MAX)VOL(MAX)) / IOL = (5.5-0.4) / 3 mA = 1.7 k
In a 400 kHz system, a minimum rise time specification of 300 nsec exists and in a 100 kHz
system, the specification is 1000 nsec.
Because R
P must pull the bus up against the total capacitance CB with a maximum rise time of
300 nsec to 0.7 V
DD, the maximum resistance for RP must be less than:
R
P(MAX) = -tR / CB * ln(1 – (VIL(MAX) – VDD(MAX)) = -300 nsec / (100pf * ln(1-0.7)) = 2.5 k
The maximum value for R
S is determined by the desired noise margin for the low level. RS
cannot drop enough voltage to make the device VOL plus voltage across RS more than the
maximum V
IL.
Rs(
MAX) = (VIL(MAX) – VOL(MIN)) / IOL(MAX) = (0.3 VDD-0.4) / 3 mA = 366
The SCL clock input must have a minimum high and low time for proper operation. The high and
low times of the I
2
C specification as well as the requirements of the I
2
C module, are shown in
the “Electrical Specifications” section in the specific device data sheet.
Figure 21-33: Sample Device Configuration for I
2
C Bus
RPRP
VDD + 10%
SDA
SCL
Device
CB = 10 - 400 pF
RSRS
Note: I
2
C devices with input levels related to VDD must have one common supply line
to which the pull-up resistor is also connected.

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