dsPIC30F Family Reference Manual
DS70062C-page 15-36 © 2004 Microchip Technology Inc.
15.12.1 Special Event Trigger Enable
The PWM module will always produce the special event trigger signal. This signal may
optionally be used by the A/D module. Refer to Section Section 17. “10-bit A/D Converter”
for more information on using the special event trigger.
15.12.2 Special Event Trigger Postscaler
The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postcale ratio. The
postscaler is useful when synchronized A/D conversions do not need to be performed during
every PWM cycle. The postscaler is configured by writing the SEVOPS<3:0> control bits in the
PWMCON2 SFR.
The special event output postscaler is cleared on the following events:
• Any write to the SEVTCMP register.
• Any device reset.
15.13 Operation in Device Power Saving Modes
15.13.1 PWM Operation in Sleep mode
When the device enters Sleep mode, the system clock is disabled. Since the clock for the PWM
time base is derived from the system clock source (T
CY), it will also be disabled. All enabled PWM
output pins will be frozen in the output states that were in effect prior to entering Sleep.
If the PWM module is used to control a load in a power application, it is the user’s responsibility
to put the PWM module outputs into a ‘safe’ state prior to executing the PWRSAV instruction.
Depending on the application, the load may begin to consume excessive current when the PWM
outputs are frozen in a particular output state. For example, the OVDCON register can be used
to manually turn off the PWM output pins as shown in the code example below.
; This code example drives all PWM pins to the inactive state
; before executing the PWRSAV instruction.
CLR OVDCON ; Force all PWM outputs inactive
PWRSAV #0 ; Put the device in SLEEP mode
SET.B OVDCONH ; Set POVD bits when device wakes.
The Fault A and Fault B input pins, if enabled to control the PWM pins via the FLTxCON registers,
will continue to function normally when the device is in Sleep mode. If one of the fault pins is
driven low while the device is in Sleep, the PWM outputs will be driven to the programmed fault
states in the FLTxCON register.
The fault input pins also have the ability to wake the CPU from Sleep mode. If the fault interrupt
enable bit is set (FLTxIE = 1), then the device will wake from Sleep when the fault pin is driven
low. If the fault pin interrupt priority is greater than the current CPU priority, then program
execution will start at the fault pin interrupt vector location upon wake-up. Otherwise, execution
will continue from the next instruction following the PWRSAV instruction.
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