Microchip Technology dsPIC30F - Operation in Power Saving Modes; Registers Associated with DCI

dsPIC30F Family Reference Manual
DS70069C-page 22-28 © 2004 Microchip Technology Inc.
5. Clear the CSDOM control bit (DCICON1<6>).
6. Write the TSCON and RSCON registers to determine which data time slots in the frame
are to be transmitted and received, respectively. This will depend on which data time slots
in the AC-Link protocol will be used. At a minimum, communication on slot #0 (Tag Slot)
is required. Refer to the discussion in Section 22.5.6.2 “16-bit AC-Link Mode”, Section
22.5.6.3 “20-bit AC-Link Mode” and Section 26. “Appendix” of this manual for
additional information.
7. Set the BLEN control bits (DCICON2<11:10>) to buffer the desired amount of data words.
For the single channel codec, BLEN = 00 will provide an interrupt at each data frame. A
higher value of BLEN could be used for this codec to buffer multiple samples between
interrupts.
8. If interrupts are to be used, clear the DCIIF status bit (IFS2<9>) and set the DCIIE control
bit (IEC2<9>).
9. Begin operation as described in Section 22.5.1.1 “DCI Start-up and Data Buffering”.
22.6 Operation in Power Saving Modes
22.6.1 CPU Idle Mode
The DCI module may optionally continue to operate while the CPU is in Idle mode. The DCISIDL
control bit (DCICON1<13>) determines whether the DCI module will operate when the CPU is in
Idle mode. If the DCISIDL control bit is cleared (default), the module will continue to operate
normally in Idle mode. If the DCISIDL bit is set, the module will halt when the CPU enters Idle
mode.
22.6.2 Sleep Mode
The DCI will not operate while the device is in Sleep mode if the CSCK signal is derived from the
device instruction clock, T
CY.
However, the DCI module has the ability to operate while in Sleep mode and wake the CPU when
the CSCK signal is supplied by an external device (CSCKD = 1). The DCI interrupt enable bit,
DCIIE, must be set to allow a wake-up event from Sleep mode. When the DCI interrupt flag,
DCIIF is set, the device will wake from Sleep mode. If the DCI interrupt priority level is greater
than the current CPU priority, program execution will resume from the DCI ISR. Otherwise,
execution will resume with the instruction following the PWRSAV instruction that previously
entered Sleep mode.
22.7 Registers Associated with DCI
Table 22-1 lists the registers associated with the DCI module.