dsPIC30F Family Reference Manual
DS70069C-page 22-18 © 2004 Microchip Technology Inc.
22.5.1.1 DCI Start-up and Data Buffering
Data transfers are begun by setting the DCIEN control bit (DCICON1<15>). Prior to this, the DCI
Control registers should have been initialized for the desired operating mode. (See Section
22.5.4 “Multi-Channel Operation”, Section 22.5.5 “I
2
S Operation”, and Section
22.5.6 “AC-Link Operation”)
A timing diagram for DCI startup is shown in Figure 22-7. In this example, the DCI is configured
for an 8-bit data word (WS<3:0> = 0111b) and an 8-bit data frame (COFSG<3:0> = 0000b). The
Multi-Channel mode (COFSM<1:0> = 00b) is used. The steps required to transmit and receive
data are described below.
1. The TXBUF registers should be pre-loaded with the first data to be transmitted before the
module is enabled. If the transmit data will be based on data received from the codec, then
the user can simply clear the TXBUF registers. This will transmit digital ‘silence’ until data
is first received into the RXBUF registers from the codec.
2. Enable the DCI module by setting the DCIEN bit (DCICON1<15>). If the DCI is the master
device, the data in the TXBUF registers will be transferred to the transmit buffers and
transmission of the first data frame will commence. Otherwise, the TXBUF data will be
held in the transmit buffers until a frame sync signal is received from the master device.
3. The TMPTY bit will be set immediately after the module is enabled and a DCI interrupt will
be generated, if enabled. At this time, the module is ready for the TXBUF registers to be
reloaded with data to be transferred on the second data frame. No data has been received
by the module at this time, so the TXBUF registers should be cleared again if the
transmitted data is calculated from the received data. The DCIIF status bit should be
cleared by the user in software if interrupts are enabled.
4. After the first data frame is transferred, the TMPTY bit will set, the RFUL status bit will be
set, and a DCI interrupt will occur, if enabled. This is the first data word received from the
device connected to the DCI.
5. The user reads the Receive register(s), automatically clearing the RFUL status bit. The
user software processes the received data at this time.
6. The Transmit register(s) is written with data to be transmitted during the next data frame.
The TMPTY status bit is cleared automatically when the write occurs. The write data may
be calculated from data that was received at the prior interrupt.
7. The next DCI interrupt occurs and the cycle repeats.
Figure 22-7: DCI Start-up and Data Buffering Example
7
CSCK
Data
RFUL
65432107 65432107 6
TMPTY
DCIEN
COFS
RX Word 1RXBUF
TX Word 1 TX Word 2 TX Word 3TXBUF
1 2 3 4
5 6
DCIIF
7
Word 1 Word 2
Cleared by User
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