Microchip Technology dsPIC30F - Address Register Dependencies

© 2004 Microchip Technology Inc. DS70049C-page 2-35
Section 2. CPU
CPU
2
2. Loop Length = -1
Execution will start at the first instruction in the loop (i.e., at [PC]) and will continue until the
loop end address ([PC – 2]) is pre-fetched. Since the loop end address is the second word
of the DO instruction, it will execute as a NOP but will still pre-fetch [PC]. The loop will then
execute again. This will continue as long as the loop end address [PC – 2] is pre-fetched
and the loop does not terminate. Should the value in the DCOUNT register reach zero and
on a subsequent decrement generate a borrow, the loop will terminate. However, in such a
case the initial instruction outside the loop will once again be the first loop instruction.
DO #33, end_loop ;DO is a two-word instruction
end_loop: NOP ;2nd word of DO executes as a NOP
ADD W2,W3,W4 ;First instruction in DO loop([PC])
3. Loop Length = 0
Execution will start at the first instruction in the loop (i.e., at [PC]) and will continue until the
loop end address ([PC]) is pre-fetched. If the loop is to continue, this pre-fetch will cause
the DO loop hardware to load the DOEND address ([PC]) into the PC for the next fetch
(which will be [PC] again). After the first true iteration of the loop, the first instruction in the
loop will be executed repeatedly until the loop count underflows and the loop terminates.
When this occurs, the initial instruction outside the loop will be the instruction after [PC].
DO #33, end_loop ;DO is a two-word instruction
NOP ;2nd word of DO executes as a NOP
end_loop: ADD W2,W3,W4 ;First instruction in DO loop([PC])
2.10 Address Register Dependencies
The dsPIC30F architecture supports a data space read (source) and a data space write
(destination) for most MCU class instructions. The effective address (EA) calculation by the AGU
and subsequent data space read or write, each take a period of 1 instruction cycle to complete.
This timing causes the data space read and write operations for each instruction to partially
overlap, as shown in Figure 2-21. Because of this overlap, a ‘Read-After-Write’ (RAW) data
dependency can occur across instruction boundaries. RAW data dependencies are detected and
handled at run-time by the dsPIC30F CPU.
Figure 2-21: Data Space Access Timing
ADD MOV
[W7]
[W10] [W9]++
X-Space Address W7 W10 W8 W9
ADD W0, [W7], [W10]
MOV [W8], [W9]++
[W8]
X-Space RAGU
Instruction Register
Contents
X-Space WAGU
1 Instruction Cycle (TCY)
T
CY0
T
CY1
T
CY2