© 2004 Microchip Technology Inc. DS70064C-page 17-13
Section 17. 10-bit A/D Converter
10-bit A/D
Converter
17
17.5 A/D Module Configuration
The following steps should be followed for performing an A/D conversion:
1. Configure the A/D module
• Select port pins as analog inputs ADPCFG<15:0>
• Select voltage reference source to match expected range on analog inputs
ADCON2<15:13>
• Select the analog conversion clock to match desired data rate with processor clock
ADCON3<5:0>
• Determine how many S/H channels will be used ADCON2<9:8> and ADPCFG<15:0>
• Determine how sampling will occur ADCON1<3> and ADCSSL<15:0>
• Determine how inputs will be allocated to S/H channels ADCHS<15:0>
• Select the appropriate sample/conversion sequence ADCON1<7:0> and
ADCON3<12:8>
• Select how conversion results are presented in the buffer ADCON1<9:8>
• Select interrupt rate ADCON2<5:9>
• Turn on A/D module ADCON1<15>
2. Configure A/D interrupt (if required)
• Clear ADIF bit
• Select A/D interrupt priority
The options for each configuration step are described in the subsequent sections.
17.6 Selecting the Voltage Reference Source
The voltage references for A/D conversions are selected using the VCFG<2:0> control bits
(ADCON2<15:13>). The upper voltage reference (V
REFH) and the lower voltage reference
(V
REFL) may be the internal AVDD and AVSS voltage rails or the VREF+ and VREF- input pins.
The external voltage reference pins may be shared with the AN0 and AN1 inputs on low pin count
devices. The A/D converter can still perform conversions on these pins when they are shared
with the V
REF+ and VREF- input pins.
The voltages applied to the external reference pins must meet certain specifications. Refer to the
“Electrical Specifications” section of the device data sheet for further details.
17.7 Selecting the A/D Conversion Clock
The A/D converter has a maximum rate at which conversions may be completed. An analog
module clock, T
AD, controls the conversion timing. The A/D conversion requires 12 clock periods
(12 T
AD). The A/D clock is derived from the device instruction clock or internal RC clock source.
The period of the A/D conversion clock is software selected using a 6-bit counter. There are 64
possible options for T
AD, specified by the ADCS<5:0> bits (ADCON3<5:0>). Equation 17-1 gives
the T
AD value as a function of the ADCS control bits and the device instruction cycle clock period,
T
CY.
Equation 17-1: A/D Conversion Clock Period
For correct A/D conversions, the A/D conversion clock (T
AD) must be selected to ensure a
minimum T
AD time of 154 nsec (for VDD = 5V).
The A/D converter has a dedicated internal RC clock source that can be used to perform
conversions. The internal RC clock source should be used when A/D conversions are performed
while the dsPIC30F is in Sleep mode. The internal RC oscillator is selected by setting the ADRC
bit (ADCON3<7>). When the ADRC bit is set, the ADCS<5:0> bits have no effect on the A/D
operation.
T
AD =
T
CY (ADCS + 1)
2
ADCS =
2T
AD
TCY
– 1
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