© 2004 Microchip Technology Inc. DS70066C-page 19-11
Section 19. UART
UART
19
19.5 UART Transmitter
The UART transmitter block diagram is shown in Figure 19-2. The heart of the transmitter is the
Transmit Shift register (UxTSR). The Shift register obtains its data from the transmit FIFO buffer,
UxTXREG. The UxTXREG register is loaded with data in software. The UxTSR register is not
loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is
transmitted, the UxTSR is loaded with new data from the UxTXREG register (if available).
Figure 19-2: UART Transmitter Block Diagram
Transmission is enabled by setting the UTXEN enable bit (UxSTA<10>). The actual transmission
will not occur until the UxTXREG register has been loaded with data and the Baud Rate Gener-
ator (UxBRG) has produced a shift clock (Figure 19-2). The transmission can also be started by
first loading the UxTXREG register and then setting the UTXEN enable bit. Normally when trans-
mission is first started, the UxTSR register is empty, so a transfer to the UxTXREG register will
result in an immediate transfer to UxTSR. Clearing the UTXEN bit during a transmission
will cause the transmission to be aborted and will reset the transmitter. As a result, the UxTX pin
will revert to a high-impedance state.
In order to select 9-bit transmission, the PDSEL<1:0> bits (UxMODE<2:1>) should be set to ‘11’
and the ninth bit should be written to the UTX9 bit (UxTXREG<8>). A word write should be
performed to UxTXREG so that all nine bits are written at the same time.
Note: The UxTSR register is not mapped in data memory, so it is not available to the user.
Word Write only
Word
UTX8
UxTXREG Low Byte
Load TSR
Transmit Control
– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt
UxTXIF
Data
‘0’ (Start)
‘1’ (Stop)
Parity
Parity
Generator
Transmit Shift Register (UxTSR)
16 Divider
Control
Signals
16X Baud Clock
from Baud Rate
Generator
Internal Data Bus
UTXBRK
UxTX
Note: ‘x’ denotes the UART number.
UxTX
UxMODE
UxSTA
16
or Byte
Write
Transmit FIFO
15
9
8
7
0
Note: There is no parity in the case of 9-bit data transmission.
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